74ACT161 ,4-Bit Binary Counter, Asynchronous Reset74ACT161SYNCHRONOUS PRESETTABLE 4-BIT COUNTER ■ HIGH SPEED: f = 290MHz (TYP.) at V = 5VMAX CC■ LOW ..
74ACT161PC ,Synchronous Presettable Binary CounterFunctional Descriptionplus the CEP to CP setup time of the last stage. The TCThe AC/ACT161 count in ..
74ACT161PC ,Synchronous Presettable Binary Counter74AC161 • 74ACT161 Synchronous Presettable Binary CounterNovember 1988Revised September 200374AC161 ..
74ACT161PC ,Synchronous Presettable Binary CounterFeaturesThe AC/ACT161 are high-speed synchronous modulo-16
74ACT161
4-Bit Binary Counter, Asynchronous Reset
1/13April 2001 HIGH SPEED:
fMAX = 290MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 8μA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT161 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS tecnology. It is a
4 bit binary counter with Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, (CLEAR), (LOAD), (PE) and (TE),
determine the mode of operation as shown in the
Truth Table. A LOW signal on CLEAR overrides
counting and parallel loading and sets all outputs
on LOW state. A LOW signal on LOAD overrides
counting and allows information on Parallel Data
inputs to be loaded into the flip-flop on the next
rising edge of CLOCK. With LOAD and CLEAR
HIGH, PE and TE permit counting when both are
HIGH. Conversely, a LOW signal on either PE and
TE inhibits counting.
The CARRY OUTPUT is HIGH when TE is HIGH
and counter is in state 15.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT161SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT1612/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
LOGIC DIAGRAM
74ACT1613/13
TIMING CHART
74ACT1614/13
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT1615/13
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74ACT1616/13
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT1617/13
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
