74ACT163M ,SYNCHRONOUS PRESETTABLE 4-BIT COUNTERABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7 VCCV DC Input V ..
74ACT163MTC ,Synchronous Presettable Binary Counter74AC163 • 74ACT163 Synchronous Presettable Binary CounterNovember 1988Revised February 200074AC163 ..
74ACT163PC ,Synchronous Presettable Binary Counter74AC163 • 74ACT163 Synchronous Presettable Binary CounterNovember 1988Revised February 200074AC163 ..
74ACT163SCX ,Synchronous Presettable Binary CounterFunctional DescriptionThe AC/ACT163 counts in modulo-16 binary sequence.From state 15 (HHHH) it inc ..
74ACT163SJ ,Synchronous Presettable Binary CounterFunctional DescriptionThe AC/ACT163 counts in modulo-16 binary sequence.From state 15 (HHHH) it inc ..
74ACT163SJX ,Synchronous Presettable Binary CounterFunctional DescriptionThe AC/ACT163 counts in modulo-16 binary sequence.From state 15 (HHHH) it inc ..
74HC174D ,Hex D-type flip-flop with reset; positive-edge triggerLogic diagram74HC_HCT174 All information provided in this document is subject to legal disclaimers. ..
74HC174N ,Hex D-type flip-flop with reset; positive-edge triggerPin configuration DIP16 Fig 5.
74HC174PW ,Hex D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC175D ,Quad D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC175DB ,Quad D-type flip-flop with reset; positive-edge triggerGENERAL DESCRIPTIONcorresponding output (Q ) of the flip-flop.nThe 74HC/HCT175 are high-speed Si-ga ..
74HC175N ,Quad D-type flip-flop with reset; positive-edge triggerFeatures and benefits Input levels: For 74HC175: CMOS level For 74HCT175: TTL level Four edge-t ..
74ACT163M
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
1/13April 2001 HIGH SPEED:
fMAX = 250MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 8μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTSIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT163 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS tecnology. It is a
4 bit binary counter with Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and sets all outputs on LOW state
on the next rising edge of CLOCK . A LOW signal
on LOAD overrides counting and allows
information on Parallel Data inputs to be loaded
into the flip-flop on the next rising edge of CLOCK.
With LOAD and CLEAR HIGH, PE and TE permit
counting when both are HIGH. Conversely, a
LOW signal on either PE and TE inhibits counting.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT163SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT163
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
LOGIC DIAGRAM
74ACT1633/13
TIMING CHART
74ACT1634/13
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT1635/13
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
74ACT1636/13
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(*) Voltage range is 5.0V ± 0.5V
74ACT1637/13
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivqlent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
