74ACT257MTR ,QUAD 2 CHANNEL MULTIPLEXER (3-STATE)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ACT257PC ,Quad 2-Input Multiplexer with 3-STATE OutputsFunctional Description Truth TableThe AC/ACT257 is quad 2-input multiplexer with 3-STATEOutput Sele ..
74ACT257SCX ,Quad 2-Input Multiplexer with 3-STATE OutputsFunctional Description Truth TableThe AC/ACT257 is quad 2-input multiplexer with 3-STATEOutput Sele ..
74ACT257SJX ,Quad 2-Input Multiplexer with 3-STATE OutputsFeaturesThe AC/ACT257 is a quad 2-input multiplexer with 3-
74ACT257M-74ACT257MTR
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
1/11April 2001 HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4 μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 257 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT257 is an advanced high-speed CMOS
QUAD 2-CHANNEL MULTIPLEXER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS tecnology.
It is composed of an independent 2-channel
multiplexer with common SELECT and ENABLE
(OE)inputs. It is a non-inverting multiplexer. When
the ENABLE input is held HIGH, the outputs are
forced to a high impedance state. When the
SELECT input is held LOW, "A" data is selected;
when SELECT input is held HIGH, "B" data is
selected.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT257QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT2572/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74ACT2573/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT2574/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT2575/11
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per
circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74ACT2576/11
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING CONDITIONS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING CONDITIONS (f=1MHz; 50% duty cycle)
