74ACT374 ,Octal D-Type Flip-Flop with 3-STATE Outputslogic diagram has not be used to estimate propagation delays2/1174ACT374
74ACT374B ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT NON INVERTINGlogic diagram has not be used to estimate propagation delays2/1174ACT374
74ACT374M ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT NON INVERTINGAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ACT374MSAX ,Octal D Flip-Flop with 3-STATE Outputs74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE OutputsNovember 1988Revised March 200574AC37 ..
74ACT374MTC ,Octal D Flip-Flop with 3-STATE Outputsapplicationsered Clock (CP) and Output Enable (OE) are common to
74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
1/11April 2001 HIGH SPEED:
fMAX = 260MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTSIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT374 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology.
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level); when
the OE is high the outputs go to the high
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT374OCTAL D-TYPE FLIP-FLOP
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT3742/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74ACT3743/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT3744/11
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT3745/11
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74ACT3746/11
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
