74ACT377 ,Octal D-Type Flip-Flop with Clock EnableapplicationsThe register is fully edge-triggered. The state of each D
74ACT377
Octal D-Type Flip-Flop with Clock Enable
74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable November 1988 Revised June 2001 74AC377 74ACT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The AC/ACT377 has eight edge-triggered, D-type flip-flopsI reduced by 50% CC with individual D inputs and Q outputs. The common buff- Ideal for addressable register applications ered Clock (CP) input loads all flip-flops simultaneously, Clock enable for address and data synchronization when the Clock Enable (CE) is LOW. applications The register is fully edge-triggered. The state of each D Eight edge-triggered D-type flip-flops input, one setup time before the LOW-to-HIGH clock transi- Buffered common clock tion, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior toOutputs source/sink 24 mA the LOW-to-HIGH clock transition for predictable operation. See 273 for master reset version See 373 for transparent latch version See 374 for 3-STATE version ACT377 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT377MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D –D Data Inputs 0 7 CE Clock Enable (Active LOW) Q –Q Data Outputs 0 7 CP Clock Pulse Input FACT is a trademark of . © 2001 DS009961
