74ACT74 ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR74ACT74DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED: f = 250MHz (TYP.) at V = 5VMAX CC ..
74ACT74B ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARlogic diagram has not be used to estimate propagation delays2/1274ACT74
74ACT74M ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ACT74MTC ,Dual D-Type Positive Edge-Triggered Flip-Flop74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-FlopNovember 1988Revised February 200574A ..
74ACT74MTCX ,Dual D-Type Positive Edge-Triggered Flip-Flop74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-FlopNovember 1988Revised February 200574A ..
74ACT74MTR ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARLOGIC DIAGRAM This
74HC245N ,74HC/HCT245; Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC245PW ,Octal bus transceiver; 3-stateGeneral descriptionThe 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74HC251 ,3-state
74HC251 ,3-state
74HC251 ,3-state
74HC251D ,8-input multiplexer; 3-stateLogic diagram74HC_HCT251 All information provided in this document is subject to legal disclaimers. ..
74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
1/12April 2001 HIGH SPEED:
fMAX = 250MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTSIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74ACT74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2 MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT74DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74ACT742/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74ACT743/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8V to 2.0V
74ACT744/12
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) (*) Voltage range is 5.0V ± 0.5V
74ACT745/12
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
Flip-Flop)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74ACT746/12
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
