74ACTQ652SCX ,Quiet Series Transceiver/RegisterFeaturesThe ACTQ652 consists of bus transceiver circuits with D-
74ACTQ652SC-74ACTQ652SCX
Quiet Series Transceiver/Register
74ACTQ652 Quiet Series Transceiver/Register June 1991 Revised September 2000 74ACTQ652 Quiet Series Transceiver/Register General Description Features The ACTQ652 consists of bus transceiver circuits with D-Guaranteed simultaneous switching noise level and type flip-flops, and control circuitry arranged for multiplexed dynamic threshold performance transmission of data directly from the input bus or fromGuaranteed pin-to-pin skew AC performance internal registers. Data on the A or B bus will be clocked Independent registers for A and B buses into the registers as the appropriate clock pin goes to the Multiplexed real-time and stored data HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.Outputs source/sink 24 mA TTL-compatible inputs The ACTQ652 utilizes Fairchild FACT Quiet Series tech- nology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series fea- tures GTO output control and undershoot corrector in addition to split ground bus for superior performance. Ordering Code: Order Number Package Number Package Description 74ACTQ652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACTQ652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description A –A , B –B A and B Inputs/3-STATE Outputs 0 7 0 7 CPAB, CPBA Clock Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of . © 2000 DS010933
