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74ALVCH16652DGG
16-bit transceiver/register with dual enable; 3-state
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
FEATURES In accordance with JEDEC standard no. 8-1A CMOS low power consumption MULTIBYTE flow-through pin-out architecture Low inductance, multiple supply and ground pins for
minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold Output drive capability 50 Ω transmission lines at 85°C Current drive ±24 mAat 3.0V.
DESCRIPTIONThe 74ALVCH16652 consists of 16 non-inverting bus
transceiver circuits with 3-state outputs, D-type flip-flops
and control circuitry arrangedfor multiplexed transmission
of data directly from the data bus or from the internal
storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the
internal registers, at the appropriate clock inputs
(nCPABor nCPBA) regardless of the select inputs (nSAB
and nSBA) or output enable (nOEAB and nOEBA) control
inputs.
Depending on the select inputs nSAB and nSBA data can
directly go from input to output (real-time mode) or data
can be controlled by the clock (storage mode), when OE
inputs permit this operating mode.
The output enable inputs nOEAB and nOEBA determine the
operation mode of the transceiver. When nOEAB is LOW, data transmission from nBnto nAnis possible and when
nOEBA is HIGH, no data transmission from nBnto nAn is
possible.
When nSAB and nSBA arein the real-time transfer mode,it
is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling nOEAB and
nOEBA. In this configuration each output reinforces its
input.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATAGround= 0; Tamb =25 °C; tr =tf= 2.5 ns.
Notes CPDis used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi+Σ (CL× VCC2× fo) where:= input frequency in MHz;= output load capacitance in pF;= output frequency in MHz;
VCC= supply voltage in Volts; (CL× VCC2×fo)= sum of outputs. The condition is VI= GNDto VCC.
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
FUNCTION TABLESee note1.
Notes H= HIGH voltage level;= LOW voltage level;= don’t care;= LOW-to-HIGH. The data output functions maybe enabledor disabledby various signalsat the nOEAB and nOEBA inputs. Data input
functions are always enabled, i.e., dataat the bus inputs willbe storedon every LOW-to-HIGH transitionon the clock
inputs.
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
ORDERING INFORMATION
PINNING
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
Note The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Above55 °C the value of Ptot derates linearly with 8 mW/K.
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
DC CHARACTERISTICSOver recommended operating conditions; voltages are referenced to GND (ground=0V).
Notes All typical values are measured at Tamb =25 °C. Valid for data inputs of bus hold parts.
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74AL VCH16652
AC CHARACTERISTICS FOR VCC= 2.3 TO 2.7VGround=0 V; tr =tf≤ 2.0 ns; CL =30pF.
Note All typical values are measured at Tamb =25 °C and VCC= 2.5V.
