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74AUP1G86GFNXPN/a600avaiLow-power 2-input EXCLUSIVE-OR gate
74AUP1G86GWNXPN/a23500avaiLow-power 2-input EXCLUSIVE-OR gate


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74AUP1G86GF-74AUP1G86GW
Low-power 2-input EXCLUSIVE-OR gate
1. General description
The 74AUP1G86 provides the single 2-input EXCLUSIVE-OR function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits Wide supply voltage range from 0.8 Vto 3.6V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 Vto 1.3 V) JESD8-11 (0.9 Vto 1.65V) JESD8-7 (1.2 Vto 1.95V) JESD8-5 (1.8 Vto 2.7V) JESD8-B (2.7 Vto 3.6V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
Rev. 5 — 28 June 2012 Product data sheet
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74AUP1G86GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74AUP1G86GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm
SOT886
74AUP1G86GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 11 0.5 mm
SOT891
74AUP1G86GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74AUP1G86GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
74AUP1G86GX 40 C to +125C X2SON5 X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking
74AUP1G86GW pH
74AUP1G86GM pH
74AUP1G86GF pH
74AUP1G86GN pH
74AUP1G86GS pH
74AUP1G86GX pH
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
6. Pinning information
6.1 Pinning
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Table 3. Pin description 1 1 data input 2 2 data input
GND 3 3 ground (0V) 4 4 data output
n.c. - 5 not connected
VCC 5 6 supply voltage
Table 4. Function table[1] L H H L
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +4.6 V
IOK output clamping current VO <0V 50 - mA output voltage Active mode and Power-down mode [1] 0.5 +4.6 V output current VO =0 VtoVCC - 20 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [2] -250 mW
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating conditions
VCC supply voltage 0.8 3.6 V input voltage 0 3.6 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC= 0.8 V to 3.6V 0 200 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 25 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70  VCC -- V
VCC = 0.9 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30  VCCV
VCC = 0.9 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.75  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.11 - - V
IO = 1.9 mA; VCC = 1.65 V 1.32 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.2 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 0.5 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V
[1] -- 40 A input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.8 -pF output capacitance VO = GND; VCC = 0 V - 1.7 - pF
Tamb = 40 C to +85C
VIH HIGH-level input voltage VCC = 0.8 V 0.70  VCC -- V
VCC = 0.9 V to 1.95 V 0.65  VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30  VCCV
VCC = 0.9 V to 1.95 V - - 0.35  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.7  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.03 - - V
IO = 1.9 mA; VCC = 1.65 V 1.30 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.6 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
[1] One input at VCC  0.6 V, other input at VCC or GND.
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 0.9 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V
[1] -- 50 A
Tamb = 40 C to +125C
VIH HIGH-level input voltage VCC = 0.8 V 0.75  VCC -- V
VCC = 0.9 V to 1.95 V 0.70  VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25  VCCV
VCC = 0.9 V to 1.95 V - - 0.30  VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.11- - V
IO = 1.1 mA; VCC = 1.1 V 0.6  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 0.93 - - V
IO = 1.9 mA; VCC = 1.65 V 1.17 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33  VCCV
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A
IOFF additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.75 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 1.4 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V
[1] -- 75 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
11. Dynamic characteristicsTable 8. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for test circuit see Figure9
Tamb = 25 C; CL = 5 pF
tpd propagation delay A or B to Y; see Figure8 [2]
VCC = 0.8 V - 21.2 - ns
VCC = 1.1 V to 1.3 V 2.3 5.9 13.1 ns
VCC = 1.4 V to 1.6 V 1.8 4.1 7.7 ns
VCC = 1.65 V to 1.95 V 1.5 3.3 5.9 ns
VCC = 2.3 V to 2.7 V 1.2 2.6 4.4 ns
VCC = 3.0 V to 3.6 V 1.0 2.3 4.0 ns
Tamb = 25 C; CL = 10 pF
tpd propagation delay A or B to Y; see Figure8 [2]
VCC = 0.8 V - 24.7 - ns
VCC = 1.1 V to 1.3 V 2.6 6.8 14.8 ns
VCC = 1.4 V to 1.6 V 2.2 4.8 8.7 ns
VCC = 1.65 V to 1.95 V 1.8 3.9 6.7 ns
VCC = 2.3 V to 2.7 V 1.5 3.1 5.2 ns
VCC = 3.0 V to 3.6 V 1.3 2.9 4.8 ns
Tamb = 25 C; CL = 15 pF
tpd propagation delay A or B to Y; see Figure8 [2]
VCC = 0.8 V - 28.2 - ns
VCC = 1.1 V to 1.3 V 3.0 7.6 16.5 ns
VCC = 1.4 V to 1.6 V 2.4 5.3 9.6 ns
VCC = 1.65 V to 1.95 V 2.1 4.4 7.5 ns
VCC = 2.3 V to 2.7 V 1.8 3.6 5.9 ns
VCC = 3.0 V to 3.6 V 1.6 3.3 5.4 ns
Tamb = 25 C; CL = 30 pF
tpd propagation delay A or B to Y; see Figure8 [2]
VCC = 0.8 V - 38.5 - ns
VCC = 1.1 V to 1.3 V 3.9 9.9 21.5 ns
VCC = 1.4 V to 1.6 V 3.2 6.9 12.5 ns
VCC = 1.65 V to 1.95 V 2.8 5.7 9.8 ns
VCC = 2.3 V to 2.7 V 2.4 4.7 7.6 ns
VCC = 3.0 V to 3.6 V 2.2 4.4 7.1 ns
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPZL and tPLZ.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
Tamb = 25 C
CPD power dissipation capacitance f = 1 MHz; VI= GND to VCC [3]
VCC = 0.8 V - 2.7 - pF
VCC = 1.1 V to 1.3 V - 2.9 - pF
VCC = 1.4 V to 1.6 V - 3.0 - pF
VCC = 1.65 V to 1.95 V - 3.1 - pF
VCC = 2.3 V to 2.7 V - 3.6 - pF
VCC = 3.0 V to 3.6 V - 4.2 - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure9
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for test circuit see Figure9
CL = 5 pF
tpd propagation delay A or B to Y; see Figure8 [1]
VCC = 1.1 V to 1.3 V 2.1 14.3 2.1 15.8 ns
VCC = 1.4 V to 1.6 V 1.6 8.8 1.6 9.7 ns
VCC = 1.65 V to 1.95 V 1.4 6.9 1.4 7.6 ns
VCC = 2.3 V to 2.7 V 1.1 5.3 1.1 5.9 ns
VCC = 3.0 V to 3.6 V 0.9 4.7 0.9 5.2 ns
CL = 10 pF
tpd propagation delay A or B to Y; see Figure8 [1]
VCC = 1.1 V to 1.3 V 2.4 16.2 2.4 17.9 ns
VCC = 1.4 V to 1.6 V 1.9 10.0 1.9 11.0 ns
VCC = 1.65 V to 1.95 V 1.7 8.0 1.7 8.8 ns
VCC = 2.3 V to 2.7 V 1.4 6.2 1.4 6.9 ns
VCC = 3.0 V to 3.6 V 1.3 5.6 1.3 6.2 ns
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
[1] tpd is the same as tPZL and tPLZ.
12. Waveforms
CL = 15 pF
tpd propagation delay A or B to Y; see Figure8 [1]
VCC = 1.1 V to 1.3 V 2.7 18.1 2.7 20.0 ns
VCC = 1.4 V to 1.6 V 2.2 11.3 2.2 12.5 ns
VCC = 1.65 V to 1.95 V 1.9 9.0 1.9 9.9 ns
VCC = 2.3 V to 2.7 V 1.6 7.0 1.6 7.7 ns
VCC = 3.0 V to 3.6 V 1.5 6.4 1.5 7.1 ns
CL = 30 pF
tpd propagation delay A or B to Y; see Figure8 [1]
VCC = 1.1 V to 1.3 V 3.5 24.1 3.5 26.6 ns
VCC = 1.4 V to 1.6 V 2.8 14.8 2.8 16.3 ns
VCC = 1.65 V to 1.95 V 2.5 11.7 2.5 12.9 ns
VCC = 2.3 V to 2.7 V 2.2 9.1 2.2 10.1 ns
VCC = 3.0 V to 3.6 V 2.1 8.3 2.1 9.2 ns
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit see Figure9
Table 10. Measurement points
0.8 V to 3.6 V 0.5  VCC 0.5  VCC VCC  3.0 ns
NXP Semiconductors 74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M
Table 11. Test data
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2  VCC
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