74CBTLV16211CZRDR ,Low-Voltage 24-Bit FET Bus Switch 54-BGA MICROSTAR JUNIOR -40 to 85 SCDS204 − JULY 2005 Member of the Texas Instruments L ..
74CBTLV16211GRG4 ,Low-Voltage 24-Bit FET Bus Switch 56-TSSOP -40 to 85 SCDS043I − DECEMBER 1997 − REVISED OCTOBER 2003DGG, DGV, ..
74CBTLV16212DLRG4 ,Low-Voltage 24-Bit FET Bus-Exchange Switch 56-SSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
74CBTLV16212GRE4 ,Low-Voltage 24-Bit FET Bus-Exchange Switch 56-TSSOP -40 to 85 SCDS044I − DECEMBER 1997 − REVISED OCTOBER 2003 ..
74CBTLV16212GRG4 ,Low-Voltage 24-Bit FET Bus-Exchange Switch 56-TSSOP -40 to 85 SCDS044I − DECEMBER 1997 − REVISED OCTOBER 2003 ..
74CBTLV1G125DBVRE4 ,Low-Voltage Single FET Bus Switch 5-SOT-23 -40 to 85maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
74HC86D ,Quad 2-input EXCLUSIVE-OR gateLogic diagram (one gate) Fig 3. IEC logic symbol74HC_HCT86 All information provided in this documen ..
74HC86DB ,Quad 2-input EXCLUSIVE-OR gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC86N ,Quad 2-input EXCLUSIVE-OR gateLogic diagram (one gate) Fig 3. IEC logic symbol74HC_HCT86 All information provided in this documen ..
74HC86PW ,Quad 2-input EXCLUSIVE-OR gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC86PW ,Quad 2-input EXCLUSIVE-OR gatePin configuration DIP14, SO14 and (T)SSOP145.2 Pin description Table 2. Pin descriptionSymbol Pin D ..
74HC86PW ,Quad 2-input EXCLUSIVE-OR gatePin configuration DIP14, SO14 and (T)SSOP145.2 Pin description Table 2. Pin descriptionSymbol Pin D ..
74CBTLV16211CGRDR-74CBTLV16211CZRDR
Low-Voltage 24-Bit FET Bus Switch 54-BGA MICROSTAR JUNIOR -40 to 85
Ioff Supports Partial-Power-Down ModeOperation
description/ordering informationThe SN74CBTLV16211C provides 24 bits of high-speed bus switching. The low on-state resistance of the switch
allows connections to be made with minimal propagation delay.
The device is organized as dual 12-bit bus switches with separate output-enable (OE) inputs. It can be used
as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is on,
and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists
between the two ports.
This device is fully specified for partial-power-down applications using Ioff . The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
