74HC132N-74HCT132DB-74HCT132N-74HCT132PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT132DB ,Quad 2-input NAND Schmitt triggerApplications Wave and pulse shapers Astable multivibrators Monostable multivibrators74HC132; 74H ..
74HCT132N ,Quad 2-input NAND Schmitt triggerGeneral descriptionThe 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible ..
74HCT132PW ,Quad 2-input NAND Schmitt triggerPin configuration DIP14, SO14 and (T)SSOP146.2 Pin description Table 2. Pin descriptionSymbol Pin D ..
74HCT137D ,3-to-8 line decoder/demultiplexer with address latches; inverting
74HCT137N ,3-to-8 line decoder/demultiplexer with address latches; inverting
74HCT138 ,3-to-8 LINE DECODER/ DEMULTIPLEXER
74VHC08MTCX_NL ,Quad 2-Input AND GateFeaturesThe VHC08 is an advanced high speed CMOS 2 Input

74HC132N-74HCT132DB-74HCT132N-74HCT132PW
Quad 2-input NAND Schmitt trigger
1. General description
The 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A
The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt trigger inputs. This
device features reduced input threshold levels to allow interfacing to TTL logic levels.
Inputs also include clamp diodes that enable the use of current limiting resistors to
interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly
changing input signals into sharply defined jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
3. Applications Wave and pulse shapers Astable multivibrators Monostable multivibrators
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Rev. 3 — 30 August 2012 Product data sheet
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
4. Ordering information
5. Functional diagram
Table 1. Ordering information
74HC132N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT132N
74HC132D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT132D
74HC132DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT132DB
74HC132PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT132PW
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care.
Table 2. Pin description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14, and (T)SSOP14
packages 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
10. Static characteristicsTable 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC132
VOH HIGH-level
output voltage = VT+ or VT
IO = 20 A; VCC = 2.0V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage = VT+ or VT
IO = 20 A; VCC = 2.0V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
ICC supply current VI = VCC or GND; IO =0A;
VCC =6.0V 2.0 - 20 - 40 A input
capacitance
-3.5 -- - - - pF
74HCT132
VOH HIGH-level
output voltage = VT+ or VT; VCC = 4.5V
IO = 20A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage = VT+ or VT; VCC = 4.5V
IO = 20 A; - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
ICC supply current VI =VCCor GND; IO = 0 A;
VCC =5.5V 2.0 - 20 - 40 A
ICC additional
supply current
per input pin; =VCC 2.1 V; IO =0A;
other inputs at VCC or GND;
VCC= 4.5Vto 5.5V 30 108 - 135 - 147 A input
capacitance
-3.5 -- - - - pF
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W): =CPD VCC2fi N+  (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;(CL VCC2fo)= sum of outputs.
Table 7. Dynamic characteristics
GND=0 V; CL=50 pF; for load circuit see Figure6.
74HC132
tpd propagation delay nA, nB to nY; see Figure5 [1]
VCC = 2.0 V - 36 125 155 190 ns
VCC = 4.5 V - 13 25 31 38 ns
VCC = 5.0 V; CL =15pF - 11 - - - ns
VCC = 6.0 V - 10 21 26 32 ns transition time see Figure5 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance
per package; VI =GNDto VCC [3] -24- - - pF
74HCT132
tpd propagation delay nA, nB to nY; see Figure5 [1]
VCC = 4.5 V - 20 33 41 50 ns
VCC = 5.0 V; CL =15pF - 17 - - - ns transition time VCC = 4.5 V; see Figure5 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance
per package; =GNDto VCC 1.5V
[3] -20- - - pF
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
12. Waveforms
Table 8. Measurement points
74HC132 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT132 1.3V 1.3V 0.1VCC 0.9VCC
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
13. Transfer characteristics
14. Transfer characteristics waveforms
Table 9. Test data
74HC132 VCC 6.0 ns 15 pF, 50pF tPLH, tPHL
74HCT132 3.0V 6.0 ns 15 pF, 50pF tPLH, tPHL
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 7 and Figure8.
74HC132
VT+ positive-going
threshold
voltage
VCC = 2.0 V 0.7 1.18 1.5 0.7 1.5 0.7 1.5 V
VCC = 4.5 V 1.7 2.38 3.15 1.7 3.15 1.7 3.15 V
VCC = 6.0 V 2.1 3.14 4.2 2.1 4.2 2.1 4.2 V
VT negative-going
threshold
voltage
VCC = 2.0 V 0.3 0.63 1.0 0.3 1.0 0.3 1.0 V
VCC = 4.5 V 0.9 1.67 2.2 0.9 2.2 0.9 2.2 V
VCC = 6.0 V 1.2 2.26 3.0 1.2 3.0 1.2 3.0 V hysteresis
voltage
VCC = 2.0 V 0.2 0.55 1.0 0.2 1.0 0.2 1.0 V
VCC = 4.5 V 0.4 0.71 1.4 0.4 1.4 0.4 1.4 V
VCC = 6.0 V 0.6 0.88 1.6 0.6 1.6 0.6 1.6 V
74HCT132
VT+ positive-going
threshold
voltage
VCC = 4.5 V 1.2 1.41 1.9 1.2 1.9 1.2 1.9 V
VCC = 5.5 V 1.4 1.59 2.1 1.4 2.1 1.4 2.1 V
VT negative-going
threshold
voltage
VCC = 4.5 V 0.5 0.85 1.2 0.5 1.2 0.5 1.2 V
VCC = 5.5 V 0.6 0.99 1.4 0.6 1.4 0.6 1.4 V hysteresis
voltage
VCC = 4.5 V 0.4 0.56 - 0.4 - 0.4 - V
VCC = 5.5 V 0.4 0.60 - 0.4 - 0.4 - V
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd =fi(tr ICC(AV) +tf ICC(AV)) VCC where:
Padd= additional power dissipation (W);= input frequency (MHz); =rise time (ns); 10 %to90%;= fall time (ns); 90%to10%;
ICC(AV)= average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 11
and Figure 12.
An example of a relaxation circuit using the 74HC132; 74HCT132 is shown in Figure 13.

Partno	Mfg	Dc	Qty	Available	Descript
74HC132N	FAI	N/a	680	avai	Quad 2-input NAND Schmitt trigger
74HCT132DB	NXP	N/a	12000	avai	Quad 2-input NAND Schmitt trigger
74HCT132N	NXP	N/a	992	avai	Quad 2-input NAND Schmitt trigger
74HCT132PW	NXP	N/a	301	avai	Quad 2-input NAND Schmitt trigger