74HCT166DB ,8-bit parallel-in/serial-out shift registerapplicationstransition, parallel data is entered into the register. When• Synchronous serial data i ..
74HCT166N ,74HC/HCT166; 8-bit parallel-in/serial-out shift registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
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74HC166D-74HC166DB-74HC166N-74HCT166D-74HCT166DB-74HCT166N
74HC/HCT166; 8-bit parallel-in/serial-out shift register
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
FEATURES Synchronous parallel-to-serial applications Synchronous serial data input for easy expansion Clock enable for “do nothing” mode Asynchronous master reset For asynchronous parallel data load see “165” Output capability: standard ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q0
from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0 → Q1 → Q2, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q7 output to the Ds input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATAGND= 0 V; Tamb =25 °C; tr =tf= 6 ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:= input frequency in MHz= output frequency in MHz
∑ (CL × VCC2 × fo)= sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
ORDERING INFORMATION
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
PIN DESCRIPTION
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
FUNCTION TABLE
Notes H= HIGH voltage level= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition= LOW voltage level= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition= lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition= don’t care= LOW-to-HIGH CP transition
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HCGND= 0 V; tr =tf= 6 ns; CL= 50 pF