74HC574D-74HC574N-74HC574PW-74HCT574PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HC574PW ,74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-stateFeatures and benefits 3-state non-inverting outputs for bus oriented
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74HC574D-74HC574N-74HC574PW-74HCT574PW
74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-state
1. General description
The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC574; 74HCT574 are octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition. When OE is LOW the contents of the 8 flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of
the OE input does not affect the state of the flip-flops.
The 74HC574; 74HCT574 is functionally identical to: 74HC564: but has non-inverting outputs 74HC374; 74HCT374: but has a different pin arrangement
2. Features and benefits 3-state non-inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from −40 °Cto+85 °C and from −40 °Cto+125°C
3. Ordering information
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 5 — 25 April 2012 Product data sheet
Table 1. Ordering information
74HC574N −40°Cto +125°C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT574N
74HC574D −40°Cto +125°C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HCT574D
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
4. Functional diagram
74HC574DB −40°Cto +125°C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74HCT574DB
74HC574PW −40°Cto +125°C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HCT574PW
Table 1. Ordering information …continued
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;= LOW voltage level;= LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;= high-impedance OFF-state;= LOW-to-HIGH clock transition.
7. Limiting values
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70°C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70°C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60°C.
Table 2. Pin description 1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0V) 11 clock input (LOW-to-HIGH, edge triggered)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
VCC 20 supply voltage
Table 3. Function table[1]
Load and read register L ↑ lL L ↑ hH H
Load register and disable output H ↑ lL Z ↑ hH Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI >VCC +0.5 V - ±20 mA
IOK output clamping current VO< −0.5 V or VO >VCC +0.5V - ±20 mA output current VO = −0.5 V to (VCC +0.5V) - ±35 mA
ICC supply current - +70 mA
IGND ground current - −70 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation DIP20 package [1]- 750 mW
SO20, SSOP20 and TSSOP20 packages [2]- 500 mW
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC574
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −20 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −20 μA; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= −6.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= −7.8 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 6.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 7.8 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current =VIHor VIL; =VCCor GND;
VCC =6.0V ±0.5 - ±5.0 - ±10.0 μA
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 μA input
capacitance
-3.5 - pF
74HCT574
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= −20μA 4.4 4.5 - 4.4 - 4.4 - V=−6 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20μA - 0 0.1 - 0.1 - 0.1 V= 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current =VIHor VIL; VCC =5.5V; =VCC or GND per input
pin; other inputs at VCC or
GND; IO =0A ±0.5 - ±5.0 - ±10 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 μA
ΔICC additional
supply current =VCC− 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; Dn inputs - 50 180 - 225 - 245 μA
per input pin; OE input - 125 450 - 563 - 613 μA
per input pin; CP input - 150 540 - 675 - 735 μA input
capacitance
-3.5 - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
10. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
For type 74HC574
tpd propagation
delay
CP to Qn; see Figure7 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 35 - 45 ns
VCC =5V; CL =15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
ten enable time OE to Qn; see Figure9 [2]
VCC = 2.0 V - 44 140 - 175 - 210 ns
VCC = 4.5 V - 16 28 - 35 - 42 ns
VCC = 6.0 V - 13 24 - 30 - 36 ns
tdis disable time OE to Qn; see Figure9 [3]
VCC = 2.0 V - 39 125 - 155 - 190 ns
VCC = 4.5 V - 14 25 - 31 - 38 ns
VCC = 6.0 V - 11 21 - 26 - 32 ns transition
time
Qn; see Figure7 [4]
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns pulse width CP HIGH or LOW;
see Figure8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
tsu set-up time Dn to CP; see Figure8
VCC = 2.0 V 60 6 - 75 - 90 - ns
VCC = 4.5 V 12 2 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns hold time Dn to CP; see Figure8
VCC = 2.0 V 5 0 - 5 - 5 - ns
VCC = 4.5 V 5 0 - 5 - 5 - ns
VCC = 6.0 V 5 0 - 5 - 5 - ns
fmax maximum
frequency
CP; see Figure7
VCC = 2.0 V 6.0 37 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 112 - 24 - 20 - MHz
VCC =5V; CL=15pF - 123 - - - - - MHz
VCC = 6.0 V 35 133 - 28 - 24 - MHz
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] tt is the same as tTHL and tTLH.
[5] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi×N+ (CL× VCC2× fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL× VCC2×fo)= sum of outputs.
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[5] -22 - - - - - pF
For type 74HCT574
tpd propagation
delay
CP to Qn; see Figure7 [1]
VCC = 4.5 V - 18 33 - 41 - 50 ns
VCC =5V; CL =15pF - 15 - - - - - ns
ten enable time OE to Qn; see Figure9 [2]
VCC = 4.5 V - 19 33 - 41 - 50 ns
tdis disable time OE to Qn; see Figure9 [3]
VCC = 4.5 V - 16 28 - 35 - 42 ns transition
time
Qn; see Figure7 [4]
VCC = 4.5 V - 5 12 - 15 - 18 ns pulse width CP HIGH or LOW;
see Figure8
VCC = 4.5 V 16 7 - 20 - 24 - ns
tsu set-up time Dn to CP; see Figure8
VCC = 4.5 V 12 3 - 15 - 18 - ns hold time Dn to CP; see Figure8
VCC = 4.5 V 5 −1- 5 - 5 - ns
fmax maximum
frequency
CP; see Figure7
VCC = 4.5 V 30 69 - 24 - 20 - MHz
VCC =5V; CL =15pF - 76 - - - - - MHz
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[5] -25 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
NXP Semiconductors 74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Table 8. Measurement points
74HC574 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT574 1.3V 1.3V 0.1VCC 0.9VCC

Partno	Mfg	Dc	Qty	Available	Descript
74HC574D	PH	N/a	2586	avai	74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-state
74HC574N	NSC	N/a	3	avai	Octal D-type flip-flop; positive edge-trigger; 3-state
74HC574PW	NXP	N/a	44857	avai	74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-state
74HCT574PW	NXP	N/a	51	avai	Octal D-type flip-flop; positive edge-trigger; 3-state