74HC590D Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC590D
8-bit binary counter with output register; 3-state
General descriptionThe 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low
power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The
storage register has parallel (Q0 to Q7) outputs. The binary counter features a master
reset counter (MRC) and count enable (CE) inputs. The counter and storage register have
separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are
connected together, the counter state always is one count ahead of the register. Internal
circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided
for cascading. Cascading is accomplished by connecting RCO of the ﬁrst stage to CE of
the second stage. Cascading for larger count chains can be accomplished by connecting
RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks
are connected together, the counter state always is one count ahead of the register. Features Counter and register have independent clock inputs Counter has master reset Complies with JEDEC standard no. 7A Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101C exceeds 2000 V Speciﬁed from −40 °Cto+85 °C and from −40°Cto +125°C Ordering information
74HC590
8-bit binary counter with output register; 3-state
Rev. 02 — 28 April 2009 Product data sheet
Table 1. Ordering information
74HC590N −40 °C to +125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC590D −40 °C to +125°C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC590PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
74HC590BQ −40 °C to +125°C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
quad ﬂat package; no leads; 16 terminals; body
2.5× 3.5× 0.85 mm
SOT763-1
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state Functional diagram
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
Q0 to Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0V)
RCO 9 ripple carry output (active LOW)
MRC 10 master reset counter input (active LOW)
CPC 11 counter clock input (active HIGH) 12 count enable input (active LOW)
CPR 13 register clock input (active HIGH) 14 output enable input (active LOW)
VCC 16 supply voltage
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition.
[2] RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter).
Table 3. Function table[1][2] X X X X Q outputs disable X X X X Q outputs enable ↑ X X X counter data stored into register ↓ X X X register stage is not changed X L X X counter clear
XXH L ↑ advance one count
XXH L ↓ no count X H H X no count
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70°C.
For SO16 packages: Ptot derates linearly with 8 mW/K above 70°C.
For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60°C.
For DHVQFN16 packages: Ptot derates linearly with 8 mW/K above 60°C. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V or VI >VCC+ 0.5 V [1]- ±20 mA
IOK output clamping current VO< −0.5 V or VO >VCC+ 0.5V [1]- ±20 mA output current VO = −0.5 V to VCC+ 0.5V
RCO standard output - ±25 mA
Qn bus driver output - ±35 mA
ICC supply current - 70 mA
IGND ground current −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125°C [2]
DIP16 package - 750 mW
SO16 package - 500 mW
TSSOP16 package - 500 mW
Table 5. Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Tamb ambient temperature −40 - +125 °C
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL
all outputs= −20 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −20 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −20 μA; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V
RCO standard output=−4 mA; VCC= 4.5V 4.18 4.31 - 4.13 - 4.1 - V= −5.2 mA; VCC= 6.0V 5.68 5.80 - 5.63 - 5.6 - V
Qn bus driver output= −6.0 mA; VCC= 4.5V 4.18 4.31 - 4.13 - 4.1 - V= −7.8 mA; VCC= 6.0V 5.68 5.80 - 5.63 - 5.6 - V
VOL LOW-level
output voltage =VIHorVIL
all outputs =20 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V
RCO standard output=4 mA; VCC= 4.5V - 0.17 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - 0.18 0.26 - 0.33 - 0.4 V
Qn bus driver output= 6.0 mA; VCC= 4.5V - 0.17 0.26 - 0.33 - 0.4 V= 7.8 mA; VCC= 6.0V - 0.18 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC= 6.0V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
per pin; VI =VIHor VIL; =VCC or GND;
other inputsat VCCor GND;
VCC= 6.0V ±0.5 - ±5.0 - ±10 μA
ICC supply current VI =VCCor GND; IO =0A;
VCC= 6.0V - 4.0 - 40 - 80 μA input
capacitance 3.5 - - - - - pF
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); for test circuit see Figure 15.
tpd propagation
delay
CPC to RCO; see Figure9 [1]
VCC = 2.0 V - 52 150 - 190 - 230 ns
VCC = 4.5 V - 19 30 - 38 - 45 ns
VCC = 6.0 V - 15 26 - 33 - 40 ns
CPR to Qn; see Figure10
VCC = 2.0 V - 50 140 - 175 - 210 ns
VCC = 4.5 V - 17 28 - 35 - 42 ns
VCC = 6.0 V - 14 24 - 30 - 36 ns
tPLH LOWto HIGH
propagation
delay
MRC to RCO; see Figure11
VCC = 2.0 V - 53 130 - 165 - 200 ns
VCC = 4.5 V - 18 26 - 33 - 40 ns
VCC = 6.0 V - 14 22 - 28 - 34 ns
ten enable time OE to Qn; see Figure12 [2]
VCC = 2.0 V - 28 105 - 130 - 160 ns
VCC = 4.5 V - 13 21 - 26 - 32 ns
VCC = 6.0 V - 11 18 - 22 - 27 ns
tdis disable time OE to Qn; see Figure12 [3]
VCC = 2.0 V - 28 105 - 130 - 160 ns
VCC = 4.5 V - 13 21 - 26 - 32 ns
VCC = 6.0 V - 11 18 - 22 - 27 ns pulse width CPC and CPR; HIGH or
LOW; see Figure 9 and
Figure10
VCC = 2.0 V 100 24 - 125 - 145 - ns
VCC = 4.5 V 20 9 - 25 - 29 - ns
VCC = 6.0 V 17 8 - 21 - 25 - ns
MRC; LOW; see Figure11
VCC = 2.0 V 75 28 - 95 - 110 - ns
VCC = 4.5 V 15 8 - 19 - 22 - ns
VCC = 6.0 V 13 6 - 16 - 19 - ns
tsu set-up time CPC to CPR; see Figure14
VCC = 2.0 V 100 46 - 125 - 150 - ns
VCC = 4.5 V 20 14 - 25 - 30 - ns
VCC = 6.0 V 17 10 - 21 - 26 - ns
CE to CPC; see Figure13
VCC = 2.0 V 100 44 - 125 - 150 - ns
VCC = 4.5 V 20 11 - 25 - 30 - ns
VCC = 6.0 V 17 9 - 21 - 26 - ns
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state
[1] tpd is the same as tPHL, tPLH.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo) = sum of outputs. hold time CE to CPC; see Figure13
VCC = 2.0 V 0 - - 0 - 0 - ns
VCC = 4.5 V 0 - - 0 - 0 - ns
VCC = 6.0 V 0 - - 0 - 0 - ns
trec recovery time MRC to CPC; see Figure11
VCC = 2.0 V 75 28 - 95 - 110 - ns
VCC = 4.5 V 15 7 - 19 - 22 - ns
VCC = 6.0 V 13 6 - 16 - 19 - ns
fmax maximum
frequency
CPC or CPR; see Figure9
and Figure10
VCC = 2.0 V 6.6 16 - 5.2 - 4.4 - MHz
VCC = 4.5 V 33 52 - 26 - 22 - MHz
VCC = 6.0 V 39 61 - 31 - 26 - MHz
CPD power
dissipation
capacitance= GNDto VCC [4] -44- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit see Figure 15.
NXP Semiconductors 74HC590
8-bit binary counter with output register; 3-state
11. Waveforms
Table 8. Measurement points
74HC590 VCC 0.5VCC 0.5VCC

Partno	Mfg	Dc	Qty	Available	Descript
74HC590D	NXP	N/a	36660	avai	8-bit binary counter with output register; 3-state