74HC75D-74HC75N Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC75D-74HC75N
74HC75; Quad bistable transparent latch
General descriptionThe 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC75 is speciﬁed in compliance with JEDEC
standard no. 7A.
The 74HC75 has four bistable latches. The two latches are simultaneously controlled by
one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data
enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs
(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time
prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched
outputs remain stable as long as the LEnn is LOW. Features Complementary Q and Q outputs VCC and GND on the center pins Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. Multiple package options Speciﬁed from −40 °Cto+80 °C and from −40°Cto +125 °C.
74HC75
Quad bistable transparant latch
Philips Semiconductors 74HC75 Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo) = sum of outputs. Ordering information
Table 1: Quick reference data
tPHL, tPLH propagation delay CL =15pF;
VCC =5V
nD to nQ, nQ - 11 - ns
LEnn to nQ, nQ - 11 - ns input capacitance - 3.5 - pF
CPD power dissipation
capacitance per latch= GND to VCC [1] -42 - pF
Table 2: Ordering information
74HC75N −40 °C to +125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC75D −40 °C to +125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC75DB −40 °C to +125°C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC75PW −40 °C to +125°C TSSOP16 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT403-1
Philips Semiconductors 74HC75 Functional diagram
Philips Semiconductors 74HC75 Pinning information
6.1 Pinning
Philips Semiconductors 74HC75
6.2 Pin description Functional description
7.1 Function table
[1]H= HIGH voltage level;= LOW voltage level;= lower case letters indicatethe stateofthe referenced output one set-up time priortothe HIGH-to-LOW
LEnn transition;= don’t care.
Table 3: Pin description 1 complementary latch output 1 2 data input 1 3 data input 2
LE34 4 latch enable input for latches 3 and 4 (active HIGH)
VCC 5 positive supply voltage 6 data input 3 7 data input 4 8 complementary latch output 4 9 latch output 4 10 latch output 3 11 complementary latch output 3
GND 12 ground (0V)
LE12 13 latch enable input for latches 1 and 2 (active HIGH) 14 complementary latch output 2 15 latch output 2 16 latch output 1
Table 4: Function table[1]
Data enabled H L L H
HHHL
Data latched L X q q
Philips Semiconductors 74HC75 Limiting values
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K. Recommended operating conditions
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input diode current VI < −0.5 V or VI >VCC+ 0.5 V - ±20 mA
IOK output diode current VO< −0.5 V or >VCC+ 0.5V ±20 mA output source or sink
current
VO = −0.5 V to VCC+ 0.5V - ±25 mA
ICC, IGND VCC or GND current - ±50 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation
DIP16 package [1]- 750 mW
SO16, SSOP16 and
TSSOP16 packages
[2]- 500 mW
Table 6: Recommended operating conditions
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - VCC V output voltage 0 - VCC V
tr, tf input rise and fall
times
VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
Tamb ambient
temperature
−40 - +125 °C
Philips Semiconductors 74HC75
10. Static characteristics
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb =25°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 1.2 - V
VCC= 4.5V 3.15 2.4 - V
VCC= 6.0V 4.2 3.2 - V
VIL LOW-level input voltage VCC= 2.0V - 0.8 0.5 V
VCC= 4.5V - 2.1 1.35 V
VCC= 6.0V - 2.8 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - V= −20 μA; VCC= 4.5V 4.4 4.5 - V= −20 μA; VCC= 6.0V 5.9 6.0 - V=−4 mA; VCC= 4.5V 3.98 4.32 - V= −5.2 mA; VCC= 6.0V 5.48 5.81 - V
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 V =20 μA; VCC= 4.5V - 0 0.1 V =20 μA; VCC= 6.0V - 0 0.1 V=4 mA; VCC= 4.5V - 0.15 0.26 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±0.1 μA
ICC quiescent supply current VI =VCCor GND; IO =0A;
VCC= 6.0V - 8.0 μA input capacitance - 3.5 - pF
Tamb= −40 °C to +85°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V=−4 mA; VCC= 4.5V 3.84 - - V= −5.2 mA; VCC= 6.0V 5.34 - - V
Philips Semiconductors 74HC75
VOL LOW-level output voltage VI =VIHorVIL =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V=4 mA; VCC= 4.5V - - 0.33 V= 5.2 mA; VCC= 6.0V - - 0.33 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
ICC quiescent supply current VI =VCCor GND; IO =0A;
VCC= 6.0V
--80 μA
Tamb= −40 °C to +125°C
VIH HIGH-level input voltage VCC= 2.0V 1.5 - - V
VCC= 4.5V 3.15 - - V
VCC= 6.0V 4.2 - - V
VIL LOW-level input voltage VCC= 2.0V - - 0.5 V
VCC= 4.5V - - 1.35 V
VCC= 6.0V - - 1.8 V
VOH HIGH-level output voltage VI =VIHorVIL -= −20 μA; VCC= 2.0V 1.9 - - V= −20 μA; VCC= 4.5V 4.4 - - V= −20 μA; VCC= 6.0V 5.9 - - V=−4 mA; VCC= 4.5V 3.7 - - V= −5.2 mA; VCC= 6.0V 5.2 - - V
VOL LOW-level output voltage VI =VIHorVIL - =20 μA; VCC= 2.0V - - 0.1 V =20 μA; VCC= 4.5V - - 0.1 V =20 μA; VCC= 6.0V - - 0.1 V=4 mA; VCC= 4.5V - - 0.4 V= 5.2 mA; VCC= 6.0V - - 0.4 V
ILI input leakage current VI =VCCor GND; VCC= 6.0V - - ±1.0 μA
ICC quiescent supply current VI =VCCor GND; IO =0A;
VCC= 6.0V - 160 μA
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74HC75
11. Dynamic characteristics
Table 8: Dynamic characteristics
GND= 0 V; tr=tf= 6 ns; CL= 50 pF; unless otherwise speciﬁed, see Figure 10.
Tamb = 25°C
tPHL, tPLH propagation delay to nQ
see Figure6
VCC = 2.0 V - 33 110 ns
VCC = 4.5 V - 12 22 ns
VCC = 6.0 V - 10 19 ns
VCC= 5.0 V; CL =15pF - 11 - ns
propagation delay to nQ
see Figure7
VCC = 2.0 V - 39 120 ns
VCC = 4.5 V - 14 24 ns
VCC = 6.0 V - 11 20 ns
VCC= 5.0 V; CL =15pF - 11 - ns
propagation delay
LEnn to nQ
see Figure9
VCC = 2.0 V - 33 120 ns
VCC = 4.5 V - 12 24 ns
VCC = 6.0 V - 10 20 ns
VCC= 5.0 V; CL =15pF - 11 - ns
propagation delay
LEnn to nQ
see Figure9
VCC = 2.0 V - 39 125 ns
VCC = 4.5 V - 14 25 ns
VCC = 6.0 V - 11 21 ns
VCC= 5.0 V; CL =15pF - 11 - ns
tTHL, tTLH output transition time see Figure 6 and7
VCC = 2.0 V - 19 75 ns
VCC = 4.5 V - 7 15 ns
VCC = 6.0 V - 6 13 ns enable pulse width
HIGH
see Figure9
VCC = 2.0 V 80 17 - ns
VCC = 4.5 V 16 6 - ns
VCC = 6.0 V 14 5 - ns
tsu set-up time nD to
LEnn
see Figure8
VCC = 2.0 V 60 14 - ns
VCC = 4.5 V 12 5 - ns
VCC = 6.0 V 10 4 - ns hold time nD to LEnn see Figure8
VCC = 2.0 V 3 −8- ns
VCC = 4.5 V 3 −3- ns
VCC = 6.0 V 3 −2- ns
Philips Semiconductors 74HC75
CPD power dissipation
capacitance per latch= GND to VCC [1] -42 - pF
Tamb = −40 °C to +85°C
tPHL, tPLH propagation delay to nQ
see Figure6
VCC = 2.0 V - - 140 ns
VCC = 4.5 V - - 28 ns
VCC = 6.0 V - - 24 ns
propagation delay to nQ
see Figure7
VCC = 2.0 V - - 150 ns
VCC = 4.5 V - - 30 ns
VCC = 6.0 V - - 26 ns
propagation delay
LEnn to nQ
see Figure9
VCC = 2.0 V - - 150 ns
VCC = 4.5 V - - 30 ns
VCC = 6.0 V - - 26 ns
propagation delay
LEnn to nQ
see Figure9
VCC = 2.0 V - - 155 ns
VCC = 4.5 V - - 31 ns
VCC = 6.0 V - - 26 ns
tTHL, tTLH output transition time see Figure 6 and7
VCC = 2.0 V - - 95 ns
VCC = 4.5 V - - 19 ns
VCC = 6.0 V - - 16 ns enable pulse width
HIGH
see Figure9
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
tsu set-up time nD to
LEnn
see Figure8
VCC = 2.0 V 75 - - ns
VCC = 4.5 V 15 - - ns
VCC = 6.0 V 13 - - ns hold time nD to LEnn see Figure8
VCC = 2.0 V 3 - - ns
VCC = 4.5 V 3 - - ns
VCC = 6.0 V 3 - - ns
Table 8: Dynamic characteristics …continued
GND= 0 V; tr=tf= 6 ns; CL= 50 pF; unless otherwise speciﬁed, see Figure 10.

Partno	Mfg	Dc	Qty	Available	Descript
74HC75D	PHILIPS	N/a	3143	avai	74HC75; Quad bistable transparent latch
74HC75N	MOTOROLA	N/a	12	avai	74HC75; Quad bistable transparent latch