74HCT11DB Fast Delivery |IC PHOENIX CO.,LIMITED

74HCT11DB ,74HC/HCT11; Triple 3-input AND gatePin configuration (T)SSOP145.2 Pin description Table 2. Pin description Symbol Pin Description1A, 2 ..
74HCT11N ,Triple 3-input AND gatePin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nC ..
74HCT11N ,Triple 3-input AND gatePin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nC ..
74HCT11PW ,Triple 3-input AND gateGENERAL DESCRIPTIONThe 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with l ..
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74VHC00TTR ,QUAD 2-INPUT NAND GATEABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7.0 VCCV DC Input ..
74VHC00TTR ,QUAD 2-INPUT NAND GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74VHC00TTR ,QUAD 2-INPUT NAND GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74VHC02 ,Quad 2-Input NOR GateGeneral Descriptiondue to mismatched supply and input voltages.The VHC02 is an advanced high-speed ..
74VHC02M ,Quad 2-Input NOR GateFeaturesThe VHC02 is an advanced high-speed CMOS 2-Input

74HCT11DB
Triple 3-input AND gate
General descriptionThe 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC11; 74HCT11 provides a triple 3-input AND function. Features Input levels: For 74HC11: CMOS level For 74HCT11: TTL level ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C Ordering information
74HC11; 74HCT11
Triple 3-input AND gate
Rev. 04 — 25 March 2010 Product data sheet
Table 1. Ordering information
74HC11N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT11N
74HC11D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT11D
74HC11DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT11DB
74HC11PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT11PW
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate Functional diagram Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
1A, 2A, 3A 1, 3, 9 data input
1B, 2B, 3B 2, 4, 10 data input
GND 7 ground (0 V)
1C, 2C, 3C 13, 5, 11 data input , 2Y, 3Y 12, 6, 8 data output
VCC 14 supply voltage
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
Table 3. Function selection[1]
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1]- ±20 mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1]- ±20 mA output current −0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current −50 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation [2]
DIP14 package - 750 mW
SO14 and (T)SSOP14
packages 500 mW
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate Recommended operating conditions Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V output voltage 0 - VCC 0 - VCC V
Tamb ambient temperature −40 - +125 −40 - +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
74HC11
VIH HIGH-level
input voltage
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL
IO = −20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = −20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = −20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current
VI = VCC or GND;
VCC = 6.0 V - ±0.1 - ±1 - ±1 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V - 2.0 - 20 - 40 μA
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate
10. Dynamic characteristics input
capacitance 3.5 - - - - - pF
74HCT11
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 μA 4.4 4.5 - 4.4 - 4.4 - V
IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V input leakage
current
VI = VCC or GND;
VCC = 5.5 V - ±0.1 - ±1 - ±1 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V - 2.0 - 20 - 40 μA
ΔICC additional
supply current
per input pin;
VI = VCC − 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V 100 360 - 450 - 490 μA input
capacitance 3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
74HC11
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 2.0 V - 32 100 125 150 ns
VCC = 4.5 V - 12 20 25 30 ns
VCC = 5.0 V; CL = 15 pF - 9 - - - ns
VCC = 6.0 V - 10 17 21 26 ns transition time see Figure 6 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance
per package; VI = GND to VCC [3] - 18 - - - pF
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC 2 × fi × N + ∑ (CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC 2 × fo) = sum of outputs.
11. Waveforms
74HCT11
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 4.5 V - 16 24 30 36 ns
VCC = 5.0 V; CL = 15 pF - 11 - - - ns transition time VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance
per package;
VI = GND to VCC − 1.5 V
[3] - 20 - - - pF
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Table 8. Measurement points
74HC11 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT11 1.3 V 1.3 V 0.1VCC 0.9VCC
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate
Table 9. Test data
74HC11 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT11 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
NXP Semiconductors 74HC11; 74HCT11
Triple 3-input AND gate
12. Package outline

Partno	Mfg	Dc	Qty	Available	Descript
74HCT11DB	NXP	N/a	1092	avai	74HC/HCT11; Triple 3-input AND gate