ADL5310ACPZ-REEL7 Fast Delivery |IC PHOENIX CO.,LIMITED

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ADL5310ACPZ-REEL7
120dB-range (3 nA
120 dB Range (3 nA to 3 mA)
Dual Logarithmic Converter
Rev. A
FEATURES
2 independent channels optimized for photodiode
interfacing
6-decade input dynamic range
Law conformance 0.3 dB from 3 nA to 3 mA
Temperature-stable logarithmic outputs
Nominal slope 10 mV/dB (200 mV/dec), externally scalable
Intercepts may be independently set by external resistors
User-configurable output buffer amplifiers
Single- or dual-supply operation
Space-efficient, 24-lead 4 mm × 4 mm LFCSP
Low power: < 10 mA quiescent current
APPLICATIONS
Gain and absorbance measurements
Multichannel power monitoring
General-purpose baseband log compression
PRODUCT DESCRIPTION
The ADL53101 low cost, dual logarithmic amplifier converts
input current over a wide dynamic range to a linear-in-dB
output voltage. It is optimized to determine the optical power
in wide-ranging optical communication system applications,
including control circuitry for lasers, optical switches, atten-
uators, and amplifiers, as well as system monitoring. The device
is equivalent to a dual AD8305 with enhanced dynamic range
(120 dB). While the ADL5310 contains two independent signal
channels with individually configurable transfer function
constants (slope and intercept), internal bias circuitry is shared
between channels for improved power consumption and
channel matching. Dual converters in a single, compact LFCSP
package yield space-efficient solutions for measuring gain or
attenuation across optical elements. Only a single supply is
required; optional dual-supply operation offers added flexibility.
The ADL5310 employs an optimized translinear structure that
use the accurate logarithmic relationship between a bipolar
transistor’s base emitter voltage and collector current, with
appropriate scaling by precision currents to compensate for the
inherent temperature dependence. Input and reference current
pins sink current ranging from 3 nA to 3 mA (limited to ±60 dB
between input and reference) into a fixed voltage defined by the
VSUM potential. The VSUM potential is internally set to
500 mV but may be externally grounded for dual-supply opera-
tion, and for additional applications requiring voltage inputs.
FUNCTIONAL BLOCK DIAGRAM
99k
OUT2
LOG2
VBIAS
99k
OUT1
LOG1
VBIAS
Figure 1.
The logarithmic slope is set to 10 mV/dB (200 mV/decade)
nominal and can be modified using external resistors and the
independent buffer amplifiers. The logarithmic intercepts for
each channel are defined by the individual reference currents,
which are set to 3 μA nominal for maximum input range by
connecting 665 kΩ resistors between the 2.5 V VREF pins and
the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets
the x-intercept four decades below the reference current—
typically 300 pA for a 3 µA reference.
The use of individually optimized reference currents may
be valuable when using the ADL5310 for gain or absorbance
measurements where each channel input has a different current-
range requirement. The reference current inputs
are also fully functional dynamic inputs, allowing log ratio
operation with the reference input current as the denominator.
The ADL5310 is specified for operation from –40°C to +85°C. US Patents: 4,604,532, 5,519,308. Other patents pending.
TABLE OF CONTENTS
Specifications.....................................................................................3
Absolute Maximum Ratings............................................................4
Pin Configuration and Function Descriptions.............................5
Typical Performance Characteristics.............................................6
General Structure............................................................................11
Theory..........................................................................................11
Managing Intercept and Slope..................................................12
Response Time and Noise Considerations..............................12
Applications.....................................................................................13
Calibration...................................................................................14
Minimizing Crosstalk................................................................14
Relative and Absolute Power Measurements..........................15
Characterization Methods.........................................................16
Evaluation Board............................................................................17
Outline Dimensions.......................................................................20
Ordering Guide...........................................................................20
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Ordering Guide..........................................................20
11/03—Revision 0: Initial Version
SPECIFICATIONS
VP = 5 V, VN = 0 V, TA = 25°C, RREF = 665 kΩ, and VRDZ connected to VREF, unless otherwise noted.
Table 1.

1 Other values of logarithmic intercept can be achieved by adjustment of RREF. Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.
ABSOLUTE MAXIMUM RATINGS
Table 2.

1 With paddle soldered down.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADL5310
DUAL LOG AMP
VSUM
INP1
IRF1
IRF2
INP2
VSUM
SCL1
BIN1
LOG1
LOG2
BIN2
SCL2
RDZ
OUT1
VPOSVPOSVN
OUT2
Figure 2. 24-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V, VN = 0 V, RREF = 665 kΩ, TA = 25°C, unless otherwise noted.
LOG
(V
1.610n100n1µ10µ100µ1m10m
IINP (A)
Figure 3. VLOG vs. IINP for Multiple Temperatures
LOG
(V10n100n1µ10µ100µ1m10m
IREF (A)
Figure 4. VLOG vs. IREF for Multiple Temperatures (IINP = 3 µA)
LOG
(V10n100n1µ10µ100µ1m10m
IINP (A)
RROR (dB (1
/dB))
2.010n100n1µ10µ100µ1m10m
IINP (A)
Figure 6. Law Conformance Error vs. IINP for Multiple Temperatures,
Normalized to 25°C
RROR (dB (1
/dB))
2.010n100n1µ10µ100µ1m10m
IREF (A)
Figure 7. Law Conformance Error vs. IREF for Multiple Temperatures,
Normalized to 25°C (IINP = 3 µA)
RROR (dB (1
/dB))10n100n1µ10µ100µ1m10m
IINP (A)
04415-0-008
LOG
(V10n100n1µ10µ100µ1m10m
IREF (A)
Figure 9. VLOG vs. IREF for Multiple Values of IINP,
Decade Steps from 3 nA to 3 mA
RROR (dB (1
/dB))10n100n1µ10µ100µ1m10m
IINP (A)
Figure 10. Law Conformance Error vs. IINP for Various Supply Conditions
RROR (dB (1
/dB))
2.010n100n1µ10µ100µ1m10m
IPD (A)
Figure 11. Law Conformance Error Distribution (3σ to Either Side of Mean)
RROR (dB (1
/dB))10n100n1µ10µ100µ1m10m
IREF (A)
Figure 12. Law Conformance Error vs. IREF for Multiple Values of IINP,
Decade Steps from 3 nA to 3 mA
RROR (dB (1
/dB))
2.010n100n1µ10µ100µ1m10m
IPD (A)
Figure 13. Law Conformance Error Distribution (3σ to Either Side of Mean)
RROR (dB (1
/dB))10n100n1µ10µ100µ1m10m
IPD (A)
Figure 14. Law Conformance Error Distribution (3σ to Either Side of Mean)
IZED
ESPON
SE (
10k100k1001k1M10M100M
FREQUENCY (Hz)
Figure 15. Small Signal AC Response, IINP to VOUT (AV = 1)
(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)
IZED
ESPON
SE (
10k100k1001k1M10M100M
FREQUENCY (Hz)
Figure 16. Small Signal AC Response, IREF to VOUT (AV = 1)
(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)
V rms/ H
1001k10k100k1M10M
FREQUENCY (Hz)
Figure 17. Spot Noise Spectral Density at VOUT vs. Frequency (AV = 1)
for IINP in Decade Steps from 3 nA to 3 mA
OUT
(V
TIME (µs)
Figure 18. Pulse Response—IINP to VOUT (AV = 1)
in Consecutive 1-Decade Steps
OUT
(V
TIME (µs)
Figure 19. Pulse Response—IREF to VOUT (AV = 1)
in Consecutive 1-Decade Steps
1.010n100n1µ10µ100µ1m10m1n
IINP (A)
rms
04415-0-020
Figure 20. Total Wideband Noise Voltage at VOUT vs. IINP (AV = 1)
DRIFT (mV
TEMPERATURE (°C)
Figure 21. VREF Drift vs. Temperature (3σ to Either Side of Mean)
Normalized to 25°C
DRIFT (mV/dec)
TEMPERATURE (°C)
Figure 22. Slope Drift vs. Temperature (3σ to Either Side of Mean)
Normalized to 25°C
DRIFT (pA)
TEMPERATURE (°C)
Figure 23. Intercept Drift vs. Temperature
(3σ to Either Side of Mean) Normalized to 25°C
INP
DRIFT (mV
TEMPERATURE (°C)
Figure 24. VINPT Drift vs. Temperature (3σ to Either Side of Mean)
Normalized to 25°C
DRIFT (mV/dec)
TEMPERATURE (°C)
Figure 25. Slope Mismatch Drift vs. Temperature
(VY1 – VY2, 3σ to Either Side of Mean) Normalized to 25°C
–50
DRIFT (pA)
TEMPERATURE (°C)
Figure 26. Intercept Mismatch Drift vs. Temperature
(IZ1 – IZ2, 3σ to Either Side of Mean) Normalized to 25°C
COUNT
SLOPE (mV/dec)
195190200205210
04415-0-027
Figure 27. Distribution of Logarithmic Slope
COUNT
INTERCEPT (pA)
200100300400500
04415-0-028
Figure 28. Distribution of Logarithmic Intercept
COUNT
VREF VOLTAGE (V)
2.482.462.502.522.54
04415-0-029
Figure 29. Distribution of VREF (RL = 100 kΩ)
COUNT0–9–6369
SLOPE MISMATCH (mV/dec)
04415-0-030
Figure 30. Distribution of Channel-to-Channel Slope Mismatch (VY1 – VY2)
COUNT
INTERCEPT MISMATCH (pA)
04415-0-031
Figure 31. Distribution of Channel-to-Channel Intercept Mismatch (IZ1 – IZ2)
COUNT0–9–6369
VINPT– VSUM VOLTAGE (mV)
04415-0-032
Figure 32. Distribution of Offset Voltage (VINPT – VSUM)

Partno	Mfg	Dc	Qty	Available	Descript
ADL5310ACPZ-REEL7 \|ADL5310ACPZREEL7	AD	N/a	555	avai	120dB-range (3 nA