CD74HC195E ,High Speed CMOS Logic 4-Bit Parallel Access RegisterMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC20E ,High Speed CMOS Logic Dual 4-Input NAND GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC195E
High Speed CMOS Logic 4-Bit Parallel Access Register
CD54HC195, CD74HC195 SCHS165E High-Speed CMOS Logic September 1997 - Revised October 2003 4-Bit Parallel Access Register Features Description • Asynchronous Master Reset The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to K, (D) Inputs to First Stage •J, [ /Title parallel, or parallel to serial data transfers at very high (CD74 speeds. • Fully Synchronous Serial or Parallel Data Transfer HC195 The two modes of operation, shift right (Q -Q ) and parallel • Shift Right and Parallel Load Capability 0 1 ) load, are controlled by the state of the Parallel Enable (PE) • Complementary Output From Last Stage input. Serial data enters the first flip-flop (Q ) via the J and K Sub- 0 / inputs when the PE input is high, and is shifted one bit in the • Buffered Inputs ject direction Q -Q -Q -Q following each Low to High clock 0 1 2 3 = 50MHz at V = 5V, (High • Typical f MAX CC transition. The J and K inputs provide the flexibility of the JK- o C = 15pF, T = 25 C L A type input for special applications and by tying the two pins Speed together, the simple D-type input for general applications. CMOS • Fanout (Over Temperature Range) The device appears as four common-clocked D flip-flops - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Logic when the PE input is Low. After the Low to High clock - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads 4-Bit transition, data on the parallel inputs (D0-D3) is transferred o o to the respective Q -Q outputs. Shift left operation (Q -Q ) Paral- • Wide Operating Temperature Range . . . -55 C to 125 C 0 3 3 2 can be achieved by tying the Q outputs to the Dn-1 inputs n lel • Balanced Propagation Delay and Transition Times and holding the PE input low. Access • Significant Power Reduction Compared to LSTTL All parallel and serial data transfers are synchronous, occurring Regis- Logic ICs after each Low to High clock transition. The ’HC195 series ter) utilizes edge triggering; therefore, there is no restriction on the • HC Types /Autho activity of the J, K, Pn and PE inputs for logic operations, other - 2V to 6V Operation than set-up and hold time requirements. A Low on the - High Noise Immunity: N = 30%, N = 30%of V at IL IH CC asynchronous Master Reset (MR) input sets all Q outputs Low, V = 5V CC independent of any other input condition. Ordering Information PInout TEMP. RANGE o PART NUMBER ( C) PACKAGE CD54HC195 (CERDIP) CD54HC195F3A -55 to 125 16 Ld CERDIP CD74HC195 (PDIP, SOIC, SOP, TSSOP) CD74HC195E -55 to 125 16 Ld PDIP TOP VIEW CD74HC195M -55 to 125 16 Ld SOIC MR 1 16 V CC CD74HC195NSR -55 to 125 16 Ld SOP J 2 15 Q 0 K 3 14 Q 1 CD74HC195PW -55 to 125 16 Ld TSSOP D0 4 13 Q 2 CD74HC195PWR -55 to 125 16 Ld TSSOP D1 5 12 Q 3 CD74HC195PWT -55 to 125 16 Ld TSSOP D2 6 11 Q 3 10 CP NOTE: When ordering, use the entire part number. The suffix R D3 7 denotes tape and reel. The suffix T denotes a small-quantity reel of 9 PE GND 8 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
