CD74HC221M96 ,High Speed CMOS Logic Dual Monostable Multivibrators with ResetFeatures Description• Overriding RESET Terminates Output Pulse The ’HC221 and CD74HCT221 are dual m ..
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CD74HC221PWR ,High Speed CMOS Logic Dual Monostable Multivibrators with ResetFeatures Description• Overriding RESET Terminates Output Pulse The ’HC221 and CD74HCT221 are dual m ..
CD74HC221PWRG4 ,High Speed CMOS Logic Dual Monostable Multivibrators with Reset 16-TSSOP -55 to 125Logic DiagramVCC16CPRN XA B R1 (9) 2 (10) 3 (11)PVCCPR2ROPDAMPRESET15 (7)-C+FFR CX XQCS RVCCMIRROR ..
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CL ,Wirewound Resistors, Commercial Power, Tab Type Terminals, Variety of core diameters and lengths, Numerous mounting hole sizes and shapes, High performance for low cost , contact ww2aresistors Document Number 3022244 Revision 04-Sep-02CLWirewound Resistors, Commercia ..
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CD74HC221-CD74HC221E-CD74HC221M96-CD74HC221PWG4-CD74HC221PWR-CD74HC221PWRG4
High Speed CMOS Logic Dual Monostable Multivibrators with Reset
CD54HC221, CD74HC221, CD74HCT221 SCHS166F High-Speed CMOS Logic November 1997 - Revised October 2003 Dual Monostable Multivibrator with Reset Features Description • Overriding RESET Terminates Output Pulse The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (R ) and an X • Triggering from the Leading or Trailing Edge [ /Title external capacitor (C ) control the timing and the accuracy X Q Buffered Outputs • Q and (CD74 for the circuit. Adjustment of R and C provides a wide X X range of output pulse widths from the Q and Q terminals. • Separate Resets HC221 Pulse triggering on the B input occurs at a particular voltage , • Wide Range of Output-Pulse Widths level and is not related to the rise and fall time of the trigger D74 C • Schmitt Trigger on B Inputs pulse. HCT22 • Fanout (Over Temperature Range) Once triggered, the outputs are independent of further trigger 1) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) /Sub- - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads and leading-edge-triggering (B) inputs are provided for o o ject C to 125 C • Wide Operating Temperature Range . . . -55 triggering from either edge of the input pulse. On power up, (High • Balanced Propagation Delay and Transition Times the IC is reset. If either Mono is not used each input (on the Speed unused device) must be terminated either high or low. • Significant Power Reduction Compared to LSTTL CMOS Logic ICs The minimum value of external resistance, R , is typically 500Ω. X Logic • HC Types The minimum value of external capacitance, C , is 0pF. The X calculation for the pulse width is t = 0.7 R C at V = 4.5V. Dual - 2V to 6V Operation W X X CC - High Noise Immunity: N = 30%, N = 30% of V Monos IL IH CC Ordering Information at V = 5V CC table o PART NUMBER TEMP. RANGE ( C) PACKAGE • HCT Types Multi- - 4.5V to 5.5V Operation CD54HC221F3A -55 to 125 16 Ld CERDIP - Direct LSTTL Input Logic Compatibility, CD74HC221E -55 to 125 16 Ld PDIP V = 0.8V (Max), V = 2V (Min) IL IH CD74HC221M -55 to 125 16 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC221MT -55 to 125 16 Ld SOIC CD74HC221M96 -55 to 125 16 Ld SOIC Pinout CD74HC221NSR -55 to 125 16 Ld SOP CD54HC221 CD74HC221PW -55 to 125 16 Ld TSSOP (CERDIP) CD74HC221PWR -55 to 125 16 Ld TSSOP CD74HC221 (PDIP, SOIC, SOP, TSSOP) CD74HC221PWT -55 to 125 16 Ld TSSOP CD74HCT221 CD74HCT221E -55 to 125 16 Ld PDIP (PDIP, SOIC) TOP VIEW CD74HCT221M -55 to 125 16 Ld SOIC CD74HCT221MT -55 to 125 16 Ld SOIC 1A 1 16 V CC CD74HCT221M96 -55 to 125 16 Ld SOIC 1B 2 15 1C R X X NOTE: When ordering, use the entire part number. The suffixes 96 1R 3 14 1C X and R denote tape and reel. The suffix T denotes a small-quantity 1Q 4 13 1Q reel of 250. 2Q 5 12 2Q 2C 6 11 2R X 2C R 7 10 2B X X GND 8 9 2A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
