DAC8043AFSZ Fast Delivery |IC PHOENIX CO.,LIMITED

DAC8043AFSZ ,12-Bit Current-Out DAC in TSSOP-8 PackageSpecifications subject to change without notice.–2– REV. ADAC8043APIN FUNCTION DESCRIPTIONSABSOLUTE ..
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DAC8043AFSZ
12-Bit Current-Out DAC in TSSOP-8 Package
REV. A
12-Bit Serial Input
Multiplying D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Compact SO-8 and TSSOP Packages
True 12-Bit Accuracy
5 V Operation @ <10�A
Fast 3-Wire Serial Input
Fast 1 �s Settling Time
2.4MHz 4-Quadrant Multiply BW
Pin-for-Pin Upgrade for DAC8043
Standard and Rotated Pinout
APPLICATIONS
Ideal for PLC Applications in Industrial Control
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration and Filters
Motion Control Systems
GENERAL DESCRIPTION
The DAC8043A is an improved high accuracy 12-bit multiply-
ing digital-to-analog converter in space-saving 8-lead packages.
Featuring serial input, double buffering and excellent analog
performance, the DAC8043A is ideal for applications where PC
board space is at a premium. Improved linearity and gain error
performance permit reduced parts count through the elimina-
tion of trimming components. Separate input clock and load
DAC control lines allow full user control of data loading and
analog output.
The circuit consists of a 12-bit serial-in/parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
Consuming only 10 µA from a single 5 V power supply, the
DAC8043A is the ideal low power, small size, high performance
solution to many application problems.
The DAC8043A is specified over the extended industrial
(–40°C to +85°C) temperature range. DAC8043A is available
in plastic DIP, and the low profile 1.75 mm height SO-8 surface
mount packages. The DAC8043AFRU is available for ultra-
compact applications in a thin 1.1 mm TSSOP-8 package.
Figure 1.Integral Nonlinearity Error vs. Code
DAC8043A–SPECIFICATIONS
REFERENCE INPUT
ANALOG OUTPUT
DIGITAL INPUTS
INTERFACE TIMING
AC CHARACTERISTICS
SUPPLY CHARACTERISTICS
NOTESUsing internal feedback resistor RFB, see Figure 19 test circuit with VREF = 10 V.These parameters are guaranteed by design and not subject to production testing.Calculated from worst case RREF: IZSE(LSB) = (RREF × ILKG × 4096)/VREF.All input control signals are specified with tR = tF = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.Calculation from en = √4KTRB where: K = Boltzmann Constant (J/°K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ VDD = 5 V, VREF = 10 V, –40�C < TA < +85�C, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
RFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Logic Inputs to GND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VIOUT to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Resistance θJA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN FUNCTION DESCRIPTIONS
*Note Pin numbers in parenthesis represent the rotated pinout of the
DAC8043A1ES and DAC8043A1FS models.
DAC8043AE/F PIN CONFIGURATIONS
DAC8043A1E AND DAC8043A1F PIN CONFIGURATION
(Rotated Pinout)
ORDERING GUIDE
NOTES
The DAC8043A contains 346 transistors. The die size measures 70.3 mil ×
57.1mil, 4014 sq mil.
*The DAC8043A1ES and DAC8043A1FS have a rotated pinout.
TSSOP-8 Package Branding:
Line 1:yww (data code: year, work week).
Line 2:8043A.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DAC8043A
Figure 2.Timing Diagram
Table I.Control-Logic Truth Table
NOTES
u positive logic transition.
The DAC Register LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the
switches in the R-2R DAC ladder.
Figure 3.Total Unadjusted Error Histogram
Typical Performance Characteristics
Figure 4.Full-Scale Output Tempco Histogram
LOGIC INPUT VOLTAGE – Volts
SUPPLY CURRENT I
mA
0.4
Figure 5.Supply Current vs. Logic Input Voltage
Figure 6.Supply Current vs. Temperature
FREQUENCY – Hz
10k
100k1M10M100M1k
2500
Figure 7.Supply Current vs. Clock Frequency
Figure 8.Power Supply Rejection vs. Frequency
Figure 9.Linearity Error vs. Digital Code
Figure 10.Linearity Error vs. External Op Amp VOS
DAC8043A
Figure 11.Midscale Transition Performance
Figure 12.Large Signal Settling Time
Figure 13.Reference Multiplying Bandwidth vs. Fre-
quency and Code
|VREF| – Volts
INL
LSB010
0.25
Figure 14.Linearity Error vs. Reference Voltage
HOURS OF OPERATION AT 150�C
NOMINAL CHANGE IN VOLTAGE
mV
100200300400500600
Figure 15.Long-Term Drift Accelerated by Burn-In
Figure 16.THD vs. Frequency

Partno	Mfg	Dc	Qty	Available	Descript
DAC8043AFSZ	AD	N/a	1	avai	12-Bit Current-Out DAC in TSSOP-8 Package