DAC8562FS-DAC8562GBC Fast Delivery |IC PHOENIX CO.,LIMITED

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DAC8562FS-DAC8562GBC
+5 Volt, Parallel Input Complete 12-Bit DAC
REV.A+5 Volt, Parallel Input
Complete 12-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
DATA
REFOUT
DGND
VOUT
AGND
VDD
CLRCE
GENERAL DESCRIPTION
The DAC8562 is a complete, parallel input, 12-bit, voltage out-
put DAC designed to operate from a single +5 volt supply. Built
using a CBCMOS process, these monolithic DACs offer the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DAC, is a rail-to-rail
amplifier, latch and reference. The reference (REFOUT) is
trimmed to 2.5 volts, and the on-chip amplifier gains up the
DAC output to 4.095 volts full scale. The user needs only sup-
ply a +5 volt supply.
The DAC8562 is coded straight binary. The op amp output
swings from 0 to +4.095 volts for a one millivolt per bit resolu-
tion, and is capable of driving ±5 mA. Built using low tempera-
ture-coefficient silicon-chrome thin-film resistors, excellent
linearity error over temperature has been achieved as shown be-
low in the linearity error versus digital input code plot.
Digital interface is parallel and high speed to interface to the
fastest processors without wait states. The interface is very sim-
ple requiring only a single CE signal. An asynchronous CLR in-
put sets the output to zero scale.
The DAC8562 is available in two different 20-pin packages,
plastic DIP and SOL-20. Each part is fully specified for opera-
tion over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
For MIL-STD-883 applications, contact your local ADI sales
office for the DAC8562/883 data sheet which specifies opera-
tion over the –55°C to +125°C temperature range.
LINEARITY ERROR — LSB
DIGITAL INPUT CODE — Decimal
Figure 1.Linearity Error vs. Digital Input Code Plot
FEATURES
Complete 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, 65 mA Drive
Very Low Power –3 mW
APPLICATIONS
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
PC Peripherals
DAC8562–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
ANALOG OUTPUT
REFERENCE OUTPUT
LOGIC INPUTS
INTERFACE TIMING SPECIFICATIONS
AC CHARACTERISTICS
SUPPLY CHARACTERISTICS
NOTES
1All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
21 LSB = 1 mV for 0 to +4.095 V output range.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ VDD = +5.0 6 5%, RS = No Load, –408C ≤ TA ≤ +858C, unless otherwise noted)
WAFER TEST LIMITS
NOTEElectrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND and AGND . . . . . . . . . . . . . . . .–0.3 V, +10 V
Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VREFOUT to AGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . .50 mA
Package Power Dissipation . . . . . . . . . . . . . .(TJ max – TA)/uJA
Thermal Resistance uJA
20-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . .74°C/W
20-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . .89°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . .150°C
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 2.Timing Diagram
Table I. Control Logic Truth Table
↑ + Positive Logic Transition; X Don't Care.
(@ VDD = +5.0 V 6 5%, RL = No Load, TA = +258C, applies to part number DAC8562GBC only,
unless otherwise noted)
DAC8562
DAC8562
Table II. Nominal Output Voltage vs. Input Code
PIN DESCRIPTIONS
PIN CONFIGURATIONS
20-Pin P-DIP
(N-20)
SOL-20
(R-20)
ORDERING GUIDE
DAC8562FP
DAC8562FS
DICE CHARACTERISTICS
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DGND
VDD
DB2
DB1
DB0
REFOUT
VOUT
AGND
NC = NO CONNECT
CLR
OPERATION
The DAC8562 is a complete ready to use 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains a voltage-switched, 12-bit, laser-trimmed
digital-to-analog converter, a curvature-corrected bandgap refer-
ence, a rail-to-rail output op amp, and a DAC register. The par-
allel data interface consists of 12 data bits, DB0–DB11, and a
active low CE strobe. In addition, an asynchronous CLR pin
will set all DAC register bits to zero causing the VOUT to be-
come zero volts. This function is useful for power on reset or
system failure recovery to a known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an out-
put that swings from AGND potential to the 2.5 volt internal
bandgap voltage. It uses a laser trimmed R-2R ladder which is
switched by N channel MOSFETs. The output voltage of the
DAC has a constant resistance independent of digital input
code. The DAC output (not available to the user) is internally
connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. The rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
RAIL-TO-RAIL
OUTPUT
BANDGAP
REFERENCE
REFOUT
2.5V
SPDT
N ch FET
SWITCHES
AV = 4.096/2.5
= 1.636V/V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
Figure 3. Equivalent DAC8562 Schematic of
Analog Portion
The op amp has a 16 μs typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the Typical Per-
formances section of this data sheet.
OUTPUT SECTION
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
Figure 4. Equivalent Analog Output Circuit
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. The voltage generated by the reference is
available at the REFOUT pin. Since REFOUT is not intended
to drive external loads, it must be buffered–refer to the applica-
tions section for more information. The equivalent emitter fol-
lower output circuit of the REFOUT pin is shown in Figure 3.
Bypassing the REFOUT pin is not required for proper opera-
tion. Figure 7 shows broadband noise performance.
POWER SUPPLY
The very low power consumption of the DAC8562 is a direct
result of a circuit design optimizing use of the CBCMOS pro-
cess. By using the low power characteristics of the CMOS for
the logic, and the low noise, tight matching of the complemen-
tary bipolar transistors, good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the DAC8562 is
strongly dependent on the actual logic-input voltage-levels
present on the DB0–DB11, CE and CLR pins. Since these in-
puts are standard CMOS logic structures, they contribute static
power dissipation dependent on the actual driving logic VOH and
VOL voltage levels. The graph in Figure 9 shows the effect on to-
tal DAC8562 supply current as a function of the actual value of
input logic voltage. Consequently for optimum dissipation use
of CMOS logic versus TTL provides minimal dissipation in the
static state. A VINL = 0 V on the DB0–DB11 pins provides the
lowest standby dissipation of 600 μA with a +5 V power supply.
DAC8562
As with any analog system, it is recommended that the
DAC8562 power supply be bypassed on the same PC card that
contains the chip. Figure 10 shows the power supply rejection
versus frequency performance. This should be taken into ac-
count when using higher frequency switched-mode power sup-
plies with ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
DAC8562 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the
DAC8562 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 11, pro-
vides information for operation below VDD = +4.75 V.
TIMING AND CONTROL
The DAC8562 has a 12-bit DAC register that simplifies inter-
face to a 12-bit (or wider) data bus. The latch is controlled by
the Chip Enable (CE) input. If the application does not involve
a data bus, wiring CE low allows direct operation of the DAC.
The data latch is level triggered and acquires data from the data
bus during the time period when CE is low. When CE goes
high, the data is latched into the register and held until CE re-
turns low. The minimum time required for the data to be
present on the bus before CE returns high is called the data
setup time (tDS) as seen in Figure 2. The data hold time (tDH) is
the amount of time that the data has to remain on the bus after
CE goes high. The high speed timing offered by the DAC8562
provides for direct interface with no wait states in all but the
fastest microprocessors.
Typical Performance Characteristics100100k10k1k
LOAD RESISTANCE – Ω
OUTPUT VOLTAGE – Volts
Figure 5.Output Swing vs. Load
TIME = 1ms/DIV
OUTPUT NOISE VOLTAGE – 500µV/DIV
Figure 8.Broadband Noise101000100
OUTPUT SINK CURRENT – µA
OUTPUT PULLDOWN VOLTAGE – mV
Figure 6.Pull-Down Voltage vs.
Output Sink Current Capability5241
LOGIC VOLTAGE VALUE – Volts
SUPPLY CURRENT – mA
Figure 9.Supply Current vs. Logic
Input Voltage
Figure 7. IOUT vs. VOUT
100100100k10k1k
POWER SUPPLY REJECTION – dB
FREQUENCY – Hz
Figure 10.Power Supply Rejection
vs. Frequency
OUTPUT LOAD CURRENT – mA
MIN – Volts
Figure 11.Minimum Supply
Voltage vs. Load
OUTPUT VOLTAGE
1mV/DIV
DATA
TIME – 10µs/DIV
Figure 14.Output Voltage Rise
Time Detail–8161012681440–2–42
TOTAL UNADJUSTED ERROR – LSB
NUMBER OF UNITS
Figure 17.Total Unadjusted
Error Histogram
TIME – 200ns/DIV
– Volts
Figure 12.Midscale Transition
Performance
Figure 15.Output Voltage Fall
Time Detail
–50 –25 0 25 50 75 100 125
TEMPERATURE – °C
FULL-SCALE OUTPUT –Volts
Figure 18.Full-Scale Voltage
vs. Temperature
Figure 13.Large Signal Settling
Time
Figure 16.Linearity Error vs.
Digital Code
Figure 19.Zero-Scale Voltage vs.
Temperature
DAC8562
0.0110100100k10k1k
FREQUENCY – Hz
OUTPUT NOISE DENSITY – µV/
Figure 20.Output Voltage Noise
Density vs. Frequency
TIME = 1µs/DIVDD
VREF
Figure 23.Reference Startup vs.
Time
TEMPERATURE – °C
SUPPLY CURRENT – mA
Figure 22.Supply Current vs.
Temperature
Figure 25.Reference Error vs.
Temperature
OUTPUT VOLTAGE CHANGE – mV
HOURS OF OPERATION AT +125°C
Figure 21.Long-Term Drift
Accelerated by Burn-In
TIME = 20µs/DIV
DATA
OUT
5mV/DIV
Figure 24.Digital Feedthrough vs.
Time
TEMPERATURE – °C
REF LINE REGULATION – %/Volt
Figure 27.Reference Line
Regulation vs. Temperature
TEMPERATURE – °C
REF LOAD REGULATION – %/mA
Figure 26.Reference Load
Regulation vs. Temperature
DAC8562–Typical Performance Characteristics

Partno	Mfg	Dc	Qty	Available	Descript
DAC8562FS	AD	N/a	480	avai	+5 Volt, Parallel Input Complete 12-Bit DAC
DAC8562GBC	PMI	N/a	718	avai	+5 Volt, Parallel Input Complete 12-Bit DAC