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DAC8800ADN/a47avaiOctal 8-Bit D/A Converter


DAC8800 ,Octal 8-Bit D/A ConverterGENERAL DESCRIPTION The DAC-EBOO TrimDAcTM is designed to be a general purpose Jigitally contro ..
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DAC8800
Octal 8-Bit D/A Converter
ANALOG
DEVICES
Octal 8-Bit CMUS
MI Converter
FEATURES
:12 LSB Total Unadjusted Error
2ws Settling Time
Serial Data Input
xFull-Scale Output Set by VREFH and VREFL
Unipolar and Bipolar Operation
TTL Input Compatible
20-Pin DIP or SOL Package
Low Cost
APPLICATIONS
. Voltage Set Point Control
. Digital Offset & GainAdjustment
. Microprocessor Controlled Calibration
. General Purpose Trimming Adjustments
FUNCTIONAL DIAGRAM
Voo VneFI-i VWEFHI
DAC-SSOO
0560080 mm A =o Vow A
ADDRESS
I I x a 8 l o vuur B
_ q "-o It c
- 13 OUT
LD LOGIC F ll 6
DAC D =-o Voor D
ADDRESS A I
tt f - DAC E =o vom a
SDI G 5mm. E "
REGISTER n I), z "O ttms, F
J 'U . _O VouTG
' 9 ‘8
i' Curt o-= DAG H -0 vour H
CLK DE 8
ll u 12 20 19
l A o 0
GND Pss CLFI VRHLG Vast“:
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However. no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents ur other rights of third parties
which may result from Its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices,
DACBBUU
The DAC-BBOO TrimDACTM is designed to be a general purpose
digitally controlled voltage adjustment device. The output
voltage range can be independently set for each set of four D/A
converters. In addition, both unipolar and bipolar output voltage
ranges are easyto establish by external reference input high and
low terminals. The digitalIy-programmed output voltages are
ideal for op amp trimming, voltage-controlled amplifier gain
setting and any general purpose trimming tasks.
A three-wire serial digital interface loads the contents of eight
internal DAC registers which establish the Output voltage levels.
An asynchronous Clear (CW) input places all DACs in a zero
code output condition, very handy for system power-up. An
internal regulator provides TTL input compatibility over a wide
range of VDD supply voltages. Single supply operation is
available by connecting Vss to GND.
ORDERING INFORMATION'
PACKAGE
OPERATING
CERDIP PLASTIC so TEMPERATURE
20-PIN 20-PIN ZO-PIN RANGE
DAC88OOBFI" - - -titVC to +125°C
DACBBOOFR DACSBOOFP DACBBOOFS" .-40'C to e85''C
I For devices processed Inlotal compliance to MlL-STW883. add (Baaalter part
number Cansull factory for 883 data sheet.
t Burn-in is available on commercial and industrial temperaturs range parts in
CerDIP and plastic DIP packages.
" Foravailabilily and burn-in information " package, contact your local sales
office
PIN CONNECTIONS
VRErLu
VREFHI 20-PIN CERDIP
"ourA ir-i'--; (R-Suffix)
v23; " 20-PIN SOL
VOUYD a (S-Suffix)
vor, ZO-PIN EPOXY DIP
sm 7 (P-Suffix)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
Mt88ilil
ELECTRICAL CHARACTERISTICS: (Note1) Unless otherwise noted, SINGLE SUPPLY: vDD " +12v, l/ss = OV, VREFH = +5v.
V L = OV; or DUAL SUPPLY: I/oo = +12v, Vss = -5V, VREFH = +2.5v, VREFL = -2.5V; F GRADE: 40%: s T, s +85''C; B GRADE:
-55°C 5 T, s +125°c.
DAC-BBOD
PARAMETEEIW SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY M specificalions apply for DACs A, B, C. D, E, F, G, H
Resolution N 8 - - Bils
't'e',n2afusted Error TUE - - al/2 LSB
Digeorte::)al Nonlinearity DNL _ - tl LSB
Full LL, Error GFSE - - :1/2 LSB
Zero Code Error 255 - - =1/2 LSB
DAC Output Resistance Rout e 12 16 k9
DAC Output Resistance "arci, ARO Ln/Ro U t - 0.5 - %
REFERENCEINPUT 't' .
REF Pins2&19 nEFL - Non-')
Voltage Range (Note 5) V
REF Pins1&20 Vss - VREFH
Input Resistance VHEF‘H Digital Inputs = 55H 2 3 - kn
Input Resistance Match ARR EFHIHR E FH Digital Inputs = 55H - 0.5 - %
Ieferenfe Inpln C Digital Inputs All Zeros - 5O 75 pF
Capaeitance (Note 4) REF Dngrtal Inputs All Ones - 75 100
DIGITAL INPUTS
Logic High IN” 24 - -
Logic Low VINL - - 0 8 V
Input Current 'm G, " 0V or oSV - - xl M
Input Capacitance (Note 4) CIN - 4 a "
Input Coding m... BINARY
POWER SUPPLIES (Note 6)
Positive Supply Curranl bn Dual Supply 2-os I 0; 0: mA
Negative Supply Current 'ss Dual Supply - 0.01 0.2 mA
Power Dissipation FDISS i:2a'fitgte,',Cltl,'n , 1: ',t, mW
le,,,':;,':,',',',':'),'' psn R AVD D =a5% - 0.001 0.01 am,
DYNAMIC PERFORMANCE (Note 4)
vou, Settling Time ts :12 LSB Error Band - 0.8 2 us
02:81:11: £2352) CT Measured Between Adjacent DAC Outputs - M) - nVs
-2- REV. A
i1Nl88ilil
ELECTRICAL CHARACTERISTICS: (Note 1) Unless otherwise noted. SINGLE SUPPLY: VDD " +12V, Vss = 0V, VREFH = +5V.
VHEFL = OV; or DUAL SUPPLY: VDD = +12v, Vss = HN, VREFH = o2.5V, vREF = -2.51t; F GRADE: -d0''C LC T, f +85°C; B GRADE:
-55t C T, s +125°C. Continued
DAC-8800
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SWFTCHING CHARACTERISTICS (Notes 4, 8)
Input Clock Pulse Width ICH, {CL Clock Level High or Low 60 - - "
Dara Setup Time to s 30 - - ns
Data Hold Time lost 30 - - ns
DAC Register Load Pulse Width ILD so - - ns
Clear Pulse Width tom 50 - - ns
Clock Edge Io Load Time tr: KIA) Stl -e - ns
Load Edge to Next Clock t 50 - - ns
Edge Time LOCK
NOTES:
1 Testing performed 1n SINGLE SUPPLY mode, except ID D' Iss, and PSRR 6. Digital Input voltages VIN = ' or VINH forTTL condition; VlN --0V or +5V for
which are tested in DUAL SUPPLY mode.
2 Includes Full Scale Error, Relative Accuracy, and Zero Code Error
3 All devices guaranteed monotonic over the full operating temperature range 7.
4. Guaranteed try design and not BU bject to production test.
5. VDD - 4 volts is the maximum reference voltage for the above spetrifications, 8.
Also VHEFH ae VREFL,
DETAILED DAC-8800 BLOCK DIAGRAM
CMOS cond Ition. DAC outputs unloaded. PD I ss is calculated tram l, D x VDD]
+ “SS x VS sl.
Measured aI VOUT pin where an adjacent V0 UT pin is making a full-scale volt-
age change.
See timing diagram tor location ot measured values.
Vao VKFHI VHEF'H VREF": mer
f', l, , 19 Tea
\__._. _----.
DAC A-D DAC E-H
REGuumn - .5v FOB INTERNAL LOGIC
LO G -tss- I Hi CK
DACA a
REGISTER NC A =o ”W"
"rr)- en
ADDRESS
ozcone nl'lfs%, DAC B -s'-o vows
o Er.ii To “owe
a f -o vamp
(/////// .4 q . r--O llorsrE
.4 ma ' " O .
A: A, N o, h tls tra o, o, tts q, q . 17 "amF
I1-EITSERIALINPUT CK “CH "--O VouuG
sm th: CK REGISTER ) me n 3O Vow”
o t tx-r,
CLKO- "
c-cur"-' NEGAYNE
SUPPLY
in la 12
tmo vss CLRtCLEAR)
REV. A _ -3-
IWl88llil
DICE CHARACTERISTICS
fi'ilfl-ll'i',-lieil)
gt-igitiitiigttgjtgiiiiii
DIE SIZE 0.151 x 0.130 Inch, 19,630 sq. mil.
(3.8354 x3.3033 mm, 12.684 sq. mm)
N-l-l-Inl—A—A—a—L-l-l
PPPT‘PVPPPT‘P
PPTIP’9‘99’P.‘
<<<<<<<
WAFER TEST LIMITS at Von = +12V, Vss = 0V, VHEFH = +5V, VREFL = 0V; TA n +25''C unless otherwise noted.
DAC-BBOOG
PARAMETER SYM BOL CONDITIONS LIMIT UNITS
Total Unadjusted Error TUE ili2 LSB MAX
Diiterential Nonlinearity DNL tl LSB MAX
Full Scale Error GFSE 11/2 LSB MAX
Zero Code Error V255 tt/2 LSB MAX
DAC Output Resistance Rcrur 1: gm:
Reference Input Resistance RpEFH Digital Inputs = 55H 2 kn MIN
Digital Inputs High VINH 2.4 V MIN
tygital Inputs Low VINL 0.8 V MAX
Digital Input Current IIN VIN = 0V or MN kl WA MAX
Positive Supply Current '00 Vss -- MN g,r, 0': mA MAX
Negative Supply Current Iss Vss _ -SV 0.2 mA MAX
'o2'(,c,',''2',,r, lull') PSRR AVDD = 15% 0.01 m MAX
Electrical Iests are performed at water probe to the limits shown. Due to variations in assembly methods and normal yield toss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate apeqications based on dice lot qualifleations through sample lot assembly and tesling.
REV. A
IlNl88ilil
AthBSQLUTEt }AXIMUM RATINGS (TA = +2500! unless PACKAGE TYPE ta (Nate t) h, UNITS
0 erWIse no e
Von to V ov, +20V 20-Pin Hermetic DIP (R) 76 11 °C/W
vDD to GND ..-.._..._P..i.._b.......-...-..-...- ov, +20v 20-Pin Plastic DIP(P) 69 27 CW
l/ss to GND ...........qPP._._...-......-...-. -20V, 0V 20-Pin so (S) 88 25 mm
Digital Input Voltage to GND -.---rrr.- GND- 0.3V. VDD + 0.3V NOTE:
VREFH tcr GND ..i.._..-...-....-.. MVREFL V001. 9'11 is specified tot worst case mounting conditions. '19.,8.A is specified for
VREFL ta GND .._......-_-r-r.. ..... ..i.....t.A......_. i','sE,''i)',ch'"CisAvi2"/r; socket for CerDIP. and P-DIP packagese.‘ is stiecmed tot device
soldered to printed circuit board for so package.
vOUT to GND ...-...-.oF..t_..o._._..-..._ VHEFL, VREFH CAUTION:
"i'irlt1iC'', 2gliggg':l.li.'.'.y.', 55°C to tl25% 1. Do nmlapply vanages higherthan VDDor iess than Vss potential on any termi-
t - ............................... - nah
Extended Industrial. DAC-8800FR,FP,FS ...-40°C to +85°C 2. The digital control inputs are zener-prutected; howsver, permanent damage
Maximum Junction Temperature (Ti Max) qr.l...-..-..- +150°C may occur on unprotected units from high-energy electrostatic fitgds. Keep
Storage Temperature... ..-65oCto +150°C units in conductive foam at all times until readyto use,
Lead Temperature (Solc'iéring' Ti' 8.90;“... 430000 3. Do ntatinsmqthisdtwieeinto powered Socksrtsirtrmoxm powerbeforeinserlion
' .. ...._..... orremoval.
Package Power Dissipation .......................... "M(Tj Max - TANG” 4. Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage [a device,
TABLE 1: PIN Function Description
PIN MNEMONIC
1 VREFL1
2 VHEFH1
4 VOUTB
5 VDUTC
6 VOUT
11 GND
12 CLR
14 vss
15 VOUTE
16 VourF
17 VOUTG
18 Vow”
19 VREFHz
20 VREFLZ
DESCRIPTION
External DAC voltage reference input shared by DAC A, B, C, D. VREFL1 determines the lowest negative DAC output voltage.
VREFL‘ must be equal to or more positive than Vss
External DAC voltage reference input shared by DAC A, B, C, D. VHEFH1 determines the highem positive DAG output voltage.
DAC A Output
DAC B Output
DAC C Output Output voltage determined by enema! VREFH1 and VR EFL1 .
DAC D Output
Positive supply, allowable input voltage range +4.5V lo +16V.
Serial Data Input
Serial Clock Input, positive edge triggered ITL Input Compatible
Clock Enable Dr Serial Clock Input, negative edge triggered
Ground
Clear Inpul (Active Low]. Asynchronous TTL compatible input that resets all DAC feglsters tty zero code.
Load DAC Register Strobe, ITL compatible input that transfers data bits from serial input register into the decoded DAC register.
See Table 2.
Negative Supply, allowable input voltage range 0V to -12V.
DAC E Output
DAC F Output
DAC G Output Output voltage determined by external VREFHZ and VREFLZ.
DAC H Output
External DAC voltage reference input shared by DAC E, F, G, H. VREFH2 determines the highest positive DAC output voltage.
External DAC voltage reference Input shared by DAC E, F, G, H. \IREFL2 determines the lowest negate DAC output voltage.
VREFLz must be equal ttt or more positive than Vss
REV. A
Illic88llll
sm,'/0(ir)szrurur)ur'araIuI
er', _/l/l/l/l/l/l/l/l/l/l/V
DAC R EG ISTE tt
LOA DEB
DETAIL SERIAL DATA INPUT TIMtNG (m =0)
(DATAINJD I "°" " jf
IUI LE ERROR mm)
c-LR INPUT (PIN 1OJT1HING IS EXACTLY INVERTED FROM CLK WPUT(P|N 9)
CLEAR OPE RATION
t1l2 L53 ERROR BAND E
FIG}! RE 1: Timing Diagrams
TABLE 2: Serial Input Decode Table
LAST h-Ftnsr
LSB MSB LSB MSB
DO D, D, D3 D, Ds th, D, A0 A, A,
, = MSB L58
L I» Ae A, A0 DAC UPDATED
MSB L58
DAC OUTPUT VOLTAGE tl o o DAG A
- Dr D: Ds D, D: D, D, Do (K _ VREFH - VREFL) o 0 1 DAC B
o 1 o DAC 0
o n o o o o o o VHEFL 0 1 1 DAC D
o o o o o o o 1 (1/256) x K ' VREFL 1 o il DAC E
E 1 o 1 mo F
1 1 o DAG G
0 1 l 1 1 1 1 1 (127/256) x K + VREFL 1 1 1 DAC H
1 O 0 o D o o O (128’256) x K + VREFL
1 o o u o o o 1 (129/256) , K + VREFL
1 1 t 1 1 1 1 1 (255/256) x K ' VREFL
TABLE 3: Logic Control Input Truth Table
CLK CLK
INPUT SHIFT REGISTER OPERATON
Shift Data
Shift Data
No Operation
IX(—l"‘
N 0 Operation
REV. A
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL UNADJUSTED ERROR
vs DIGITAL INPUT CODE
SUPPLY CURRENT "
TEMPERATURE
vm, . uzv
Vee, .-. 2MV
DACI A, B. c. n SUPERIMPO$ED
vmu. . .sv me. = w
loo -sunp LY CURRENT (mm
TOTAL UNABJU STED EH RON (LSD)
DAC. E, F, G, n SUPERIMPOSED
mm, = av va, ' W
B bt 129 Is! 256
D I GlTAL-IN PUT CODE (DE CMIAU
DAC OUTPUT SETTLING TIME
POSITIVE & NEGATIVE
TRANSITIONS
“la": 3‘]
UPPER TRACE: tur, INPUT (5V/DIV]
LOWER TRACE: VOWA (ZWDIV)
CONDITIONS: Var, = +12v, vop, = +5v,
tGert-, = W. vss = ov,
“L = 1Mt2, CL = 3.4PF
DAC OUTPUT CHANNEL-TO-
CHANNEL CROSSTALK BOTH
TRANSITIONS
'ttjr-it-tttttir-ith-std
UPPER TRACE: VOUTA 0 TO Csv" CHANGE
LOWER TRACE: voma (1V/DIV]
CONDITIONS: vlm ' +12v. VREFM‘ .-. etN,
VREFL‘ = tw, vss = av,
h = IMP, Cu = 3.#pF
REV. A
-rs -50 45 0 " 50 "
TEIA " NATURE CCI
100 M5
EXPANDED DAC OUTPUT
SETTLING TIME POSITIVE
TRANSITION
ummnug: ll m HI
UPPER Time: Td, IN-PUTF {5V/DlV)
LOWER TRACE: VoutA (mow)
CONDITIONS; vDD = e12v,v“,u‘ = sSV,
VREFL' = ov, vss = ov,
nL = 1M9. A. r, 3.4PF
EXPANDED DAC OUTPUT
CHANNEL-TO-CHANNEL CROSS-
TA LK NEGATIVE TRAN smon
uiWttrt TRACETOUTA +titf TO ov CHKNGE
LOWER TRACE: vows (1onmwmv1
CONDITIONS: vDD = .12v,vm:n1 " oSM,
VREFLi = ov, Vss = ov,
RL =1|\.1r2.cL " upF
POWER SUPPLY HEJECTION RATIO mm
DABBBUU
POWER SUPPLY REJECTION
RATIO vs FREQUENCY
. " x ‘JS'C
I ng- -5V
Yon -- +1 W
" "tl) 1k Ink look
FREQUENCY 1N1:
EXPANDED DAC OUTPUT
SETTLING TIME NEGATIVE
TRANSITION
UPPER. fKAcs: tu, INPUT (swam
LOWER TRACE: Ito UTA (IV/DIV)
CONDITIONS: VDD = +12V, VHEFH1 = +5V,
VREF t" 0V, vss = ov,
Ru =1Mn,c._ = 3.4PF
EXPANDED DAC OUTPUT
CHANN EL-TO-CHANNEL CROSS-
TALK POSITIVE TRANSITION
_ . ' ": .
iv 10w
UFPER TRACE: VOWA tiro 45v CHANGE
LOWER TRACE: vows (toomwnm
CONDITIONS: vlm = +12v. vnan1 " rsV,
VREFLI = 0V, Vss t 0V,
"L = IMO, Cu = 3.4PF
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