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DP83850CVFNSC N/a9avai100 Mb/s TX/T4 Repeater Interface Controller (100RIC⑩)


DP83850CVF ,100 Mb/s TX/T4 Repeater Interface Controller (100RIC⑩)FeaturesThe DP83850C 100 Mb/s TX/T4 Repeater Interface Con- ■ IEEE 802.3u repeater and management c ..
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DP83850CVF
100 Mb/s TX/T4 Repeater Interface Controller (100RIC⑩)
DP83850C 100 Mb/s TX/T4 Repeater Interface Contr
oller (100RIC

June 1998
DP83850C 100 Mb/s TX/T4 Repeater Interface Controller
(100RIC
)
General Description

The DP83850C 100 Mb/s TX/T4 Repeater Interface Con-
troller, known as 100RIC, is designed specifically to meet
the needs of today's high speed Ethernet networking sys-
tems. The DP83850C is fully compatible with the IEEE
802.3 repeater's clause 27.
The DP83850C supports up to twelve 100 Mb/s links with
its network interface ports. The 100RIC can be configured
to be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters with up to 372 ports may
be constructed by cascading DP83850Cs together using
the built-in Inter Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Infor-
mation Base device, a DP83850C based repeater
becomes a managed entity that is compatible with IEEE
802.3u (clause 30), collecting and providing an easy inter-
face to all the required network statistics.
System Diagram
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
DP83856
100 Mb/s
Repeater Information Base
(100RIB)

DP83223
100BASE-X
Transceiver
Port 0
100Mb/s
Ethernet
Ports
Inter Repeater Bus
RX Enable [11..0]
Management Bus
MII
DP83850C
100 Mb/s
Repeater Interface Controller
(100RIC8)

Management
I/O Devices
Program
Memory
Management
CPU
Statistics
SRAM
DP83840A
100 PHY
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
DP83223
100BASE-X
Transceiver
Port 2
DP83840A
100 PHY
DP83223
100BASE-X
Transceiver
Port 11
DP83840A
100 PHY
#11
(IR_COL, IR_DV)
(TXD[3:0], TX_ER, TX_RDY)
Features
IEEE 802.3u repeater and management compatible Supports Class II TX translational repeater and Class I
T4 repeater Supports 12 network connections (ports) Up to 31 repeater chips cascadable for larger hub appli-
cations (up to 372 ports) Separate jabber and partition state machines for each
port Management interface to DP83856 allows all repeater
MIBs to be maintained Large per-port management counters - reduces man-
agement CPU overhead On-chip elasticity buffer for PHY signal re-timing to the
DP83850C clock source Serial register interface - reduces cost Physical layer device control/status access available via
the serial register interface Detects repeater identification errors 132 pin PQFP package
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