DP83907VF ,AT/LANTIC II [Life-time buy]FeaturesYController and integrated bus interface solution for IEEEThe DP83907 Twisted-Pair Enhanced ..
DP83907VF ,AT/LANTIC II [Life-time buy]PIN DESCRIPTIONThe ENDEC module interfaces directly to the transceivermodule, and also provides a f ..
DP8390DN ,NIC Network Interface ControllerPIN DESCRIPTIONScountandcost,allbusarbitrationandmemorysupportlogicare integrated into the NIC.6.0D ..
DP8390DN. ,NIC Network Interface ControllerPIN DESCRIPTIONScountandcost,allbusarbitrationandmemorysupportlogicare integrated into the NIC.6.0D ..
DP8390DV ,NIC Network Interface ControllerELECTRICAL CHARACTERISTICSYUtilizes low power microCMOS processYIncludes15.0SWITCHING CHARACTERISTI ..
DP8390DV ,NIC Network Interface ControllerDP8390D/NS32490DNICNetworkInterfaceControllerJuly1995DP8390D/NS32490DNICNetworkInterfaceControllerG ..
DS90C032E-QML ,LVDS Quad CMOS Differential Line Receiverapplications.n Available to Standard Microcircuit Drawing (SMD)5962-95834Connection DiagramsDual-In ..
DS90C032TM ,LVDS Quad CMOS Differential Line ReceiverMICROCIRCUIT DATA SHEETOriginal Creation Date: 04/14/00MNDS90C032-X-RH REV 1B1Last Update Date: 08/ ..
DS90C032TMX ,LVDS Quad CMOS Differential Line ReceiverFeatures- High impedance LVDS inputs with power-off - Accepts small swing (330 mV) differential sig ..
DS90C032TMX/NOPB ,LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Maximum RatingsSupply Voltage (V )−0.3V to +6VCCInput Voltage (R , R )−0.3V to (V +0.3V)IN+ IN− CCE ..
DS90C032W-QMLV ,LVDS Quad CMOS Differential Line Receiver 16-CFP -55 to 125FEATURES DESCRIPTIONThe DS90C032 is a quad CMOS differential line2• Single Event Latchup (SEL) Immu ..
DS90C124IVS , 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DP83907VF
AT/LANTIC II [Life-time buy]
TL/F/12082
DP83907
AT/LANTIC
PRELIMINARY
November 1995
DP83907 AT/LANTICTMII
General Description
The DP83907 Twisted-Pair Enhanced Coaxial NetworkIn-
terface Controllerisa CMOS VLSI device designedfor easy
implementationof CSMA/CD local area networks.
Uniquetothe DP83907isthe integrationofthe entirebus
interfacefor PCATISA (Industry Standard Architecture)bus
based systems. Hardwareand software selectable options
allowthe DP83907’sbus interfacetobe configuredinthe
same mannerasan NE2000 Architecture.Allbus drivers
and control logicare integratedto reduce board costand
area.
Supported network interfaces include 10BASE5or
10BASE2 Ethernetviaan external transceiver connectedto
itsAUl port,and Twisted-pair EthernetÉ (10BASE-T) using
the on-board transceiver. The DP83907 providesthe Ether-
net Media Access Control(MAC), Encode-Decode (ENDEC)
withanAUl interface,and 10BASE-T transceiver functions accordance withthe lEEE 802.3 standards.
The DP83907’s integrated 10BASE-T transceiver fully com-
plieswiththe IEEE standard. This functional block incorpo-
ratesthe receiver, transmitter, collision, heartbeat, loop-
back, jabber,andlink integrity blocksas definedinthe stan-
dard. The transceiver when combined with equalizationre-
sistors, transmit/receive filters,and pulse transformerspro-
videsa complete physical interface fromthe DP83907’s
ENDEC moduleandthe twisted pairmedium. (continued)
Features Controllerand integratedbus interface solutionfor IEEE
802.3, 10BASE5, 10BASE2, and 10BASE-T Software compatible with industry standard Ethernet
Adapters: NovellÉ’s NE2000No externalbus logicor drivers needed Supports jumperedor jumperless configuration Provides EEPROM interfacefor non-volatile storageof
configuration data, user-defined data and Ethernet
Physical Address Allows in-situ programmingof EEPROM Integrated controller, ENDEC,and transceiver Full IEEE 802.3 compliantAUI interface Single5V supply
10BASE-T TRANSCEIVER MODULE: Integrates transceiver functionality Transmitterand receiver functions Collision detect, heartbeatand jabber Selectablelink integritytestorlink disable Polarity Detection/Correction Auto switchOn chip filter
ENDEC MODULE:10 Mbit/s Manchester encoding/decoding Squelchon receiveand collision pairs
MAC/CONTROLLER MODULE: Software compatible with DP8390, DP83901, DP83902 Efficient buffer management implementation
IN-CIRCUIT TEST
1.0 System Diagram
TL/F/12082–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
AT/LANTICTMisatrademark ofNationalSemiconductor Corporation.
EthernetÉ isaregistered trademarkof XeroxCorporation.
NetWareTMisa trademark ofNovellIncorporated.
NovellÉisa registeredtrademarkofNovell Incorporated.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
