DP8429D-70 ,4.5 V to 5.5 V, 150 mA, 1 megabit high speed dynamic RAM controller/driverElectrical Specifications, Timing Diagrams and
Test Conditions
System Diagram
DP84300
PRO ..
DP8429D-80 ,4.5 V to 5.5 V, 150 mA, 1 megabit high speed dynamic RAM controller/driverBlock Diagrams
Recommended Companion Components
Device Connection Diagrams and Pin Definitions
..
DP8431V-33 ,microCMOS Programmable 256K/1M/4M Dynamic RAM Controller/DriversFeaturesYOn chip high precision delay line to guarantee criticalTheDP8430V/31V/32VdynamicRAMcontrol ..
DP8432V-33 ,microCMOS Programmable 256K/1M/4M Dynamic RAM Controller/Driversapplications. The controllersThe RAS and CAS drivers can be configured to drive a one,incorporate a ..
DP8432V-33 ,microCMOS Programmable 256K/1M/4M Dynamic RAM Controller/DriversELECTRICAL CHARACTERISTICS13.0 AC TIMING PARAMETERS14.0 DP8430V/31V/32V USER HINTS21.0IntroductionT ..
DP8440V-40 ,microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/DriverFeaturesY40 MHz and 25 MHz operationThe DP8440/41 Dynamic RAM Controllers provide an easyYinterface ..
DS90CF383BMTX/NOPB ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 56-TSSOP -10 to 70FEATURES DESCRIPTIONThe DS90CF383B transmitter converts 28 bits of23• No Special Start-up Sequence ..
DS90CF383MTD ,+ 3.3V LVDS 24-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF384AMTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF384A receiver ..
DS90CF384AMTD. ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF384AMTD/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkFEATURES DESCRIPTIONThe DS90CF384A receiver converts the four LVDS2• 20 to 65 MHz Shift Clock Suppo ..
DS90CF384AMTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzElectrical Characteristics (Continued)Note 1: “Absolute Maximum Ratings” are those values beyond wh ..
DP8428D-70-DP8429D-70-DP8429D-80
4.5 V to 5.5 V, 150 mA, 1 megabit high speed dynamic RAM controller/driver
sz-cd ~
National
Semiconductor
Corporation
General Description
The DP8428 and DP8429 1M DRAM Controller/Drivers are
designed to provide "NoAVaitstate" CPU interface to Dy-
namic RAM arrays of up to 8 Mbytes and larger. The
DP8428 and DP8429 are tailored for 32-bit and 16-bit sys-
"Fem requirements, res ectwel . Both deuces are fabricated"
‘mmlated Advanced Low power
Schotth (ALS) Erocess and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed, level of integration, and power
consumption.
Each device integrates the following critical 1M DRAM con-
troller functions on a single monolithic device: ultra precise
delay line; 9 bit refresh counter; falI-through row, column,
and bank select input latches; Row/Column address mux-
ing logic; on-board high capacitive-Ioad R_AS, trig, Write
Enable and Address output drivers; and, precise control sig-
nal timing for all the above.
In order to specify each device for "true" worst case operat-
ing conditions, all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance. The chip's delay timing logic makes
use of a patented new delay line technique which keeps AC
skew to $3 ns over the full Vcc range of i 10% and tem-
perature range of --55oC to +125°C. The DP8428 and
DP8429 guarantee a maximum RASIN to CASOUT delay of
80 ns or 70 ns even while driving an 8 Mbyte memory array
with error correction check bits included. Two speed select-
ed options of these devices are shown in the switching
DP8428/NS32828, DP8429/NS32829
1 Megabit High Speed Dynamic RAM Controller/Drivers
January 1986
PC) s c;
0/7”er
Features
I: Makes DRAM interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Eliminates 20 discrete components for significant board
real estate reduction, system power savings and the
elimination of chip-to-chip AC skewing
On-board ultra precise delay line
On-board high capacitive R-AS, W, W and Address
drivers (specified driving 88 DRAMs directly)
AC specified for directly addressing up to 8 Mbytes
Low power/high speed bipolar oxide isolated process
Downward pin- and function compatible with 256k
DRAM Controller/Drivers DP8409A, DP8417, DP8418,
and DP8419
Contents
II System and Device Block Diagrams
II Recommended Companion Components
ll Device Connection Diagrams and Pin Definitions
ll Device Differences-DPM" vs DP8429
n Mode of Operation
(Descriptions and Timing Diagrams)
I: Application Description and Diagrams
II DC/AC Electrical Specifications, Timing Diagrams and
Test Conditions
TRI-STATE' us a registered Irademark at National Serwt;onductor Corp
PAL' Is a veguslared trademark ot and used under license with Monolllmc Memonas. Inc
characteristics section of this document. (Continued)
System Diagram
CPO " DP8428 MULTIPLEXED ADDRESS BUS '/Sf2/
32 - BIT ' DP84300 ' 0R tN-9(500 PF DRWERS) DYNAMIC RAMS
16 - BIT PROGRAMMABLE DP8429
a - BIT REFRESH TIMER -
1 mm” RAso-s (150 " DRIVERS) UP TO
, DRAM "e-""'""""-"''''"'"''-)) a MEGAEYTES
CONIROLLER/ - 3'2th
:1 Azoiszsiciryzrzx) DRIVERS CAS 600 r omv R
ADDRESS BUS ( p E ) CORRECTION,
WI (500 pF DRIVER) CHECK BITS
INTERRUPT --)y
m/m (zrrr) TRANS- t MEMORY DATA BUS > DATA m
" n GENERS
g IMML.
, ENABLE BUFFER <3: om OUT
DP84XX2
CPO SPECIFIC
REFRESH/ACCESS DP8428 29 CONTROL DP8400-2 " OP8402A ' CHECK ans m
ARBITRATlON 16 BIT OR 32 an
ERROR DETECTION
ERROR common WW2 8402A CONTROL AND CORRECTION Bum I T.., CHECK BITS OUT
ENABLE BUFFERS "
TL/F/8649-t
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Functional Block Diagrams
DP8429
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Connection Diagrams
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TL/F/8649-7
System Companion Components
Device ' Function
DP84300 Programmable Refresh Timer for DP84xx DRAM Controller
DP84412 NS32008/16/32 to DP8409A/17/18/19/28/29 Interface
DP84512 NS32332 to DP8417/18/19/28/29 Interface
DP84322 68000/08/10 to DP8409A/17/18/19/28/29 Interface (up to 8 MHz)
DP84422 68000/08/10 to DP8409A/17/18/19/28/29 Interface (up to 12.5 MHz)
DP84522 68020 to DP8417/18/19/28/29 Interface
DP84432 8086/88/186/188 to DP8409A/17/1B/19/28/29 Interface
DP84532 80286 to DP8409A/17/18/19/28/29 Interface
DP8400-2 16-Bit Expandable Error Checker/Corrector (E202)
DP8402A 32-Bit Error Detector And Corrector (EDAC)
General Description (Continued)
With its four independent ms outputs and ten multiplexed
address outputs, the DP8429 can support up to four banks
of 64k, 256k or 1M DRAMs. Two bank select pins, Bl and
BO, are decoded to activate one of the FtAS signals during
an access, leaving the three non-selected banks in the
standby mode (less than one tenth of the operating power)
with data outputs in TRl-STATEe. The DP8428's one Bank
Select pin, Bl, enables 2 banks automatically during an ac-
cess in order to provide an optimum interface for 32-bit mi-
croprocessors.
The DP8428 and DP8429 each have two mode-select pins,
allowing for two refresh modes and two access modes. Re-
fresh and access timing may be controlled either externally
or automatically. The automatic modes require a minimum
of input control signals.
A refresh counter is on-chip and is multiplexed with the row
and column inputs. lts contents appear at the address out-
puts of the DP8428 or DP8429 during any refresh, and are
incremented at the completion of the refresh. Row, Column
and bank address latches are also on-chip. However, it the
address inputs to the DP8428 or DP8429 are valid through-
out the duration of the access, these latches may be operat-
ed in the falMhrough mode.
Each device is available in either the 52 pin Ceramic DIP, or
the low cost JEDEC standard 68 pin Plastic Chip Carrier
(PCC) package.
DP8428 vs DP8429
The DP8428 DYNAMIC RAM CONTROLLER/DRIVER is
identical to the DP8429 with the exception of two functional
differences incorporated to improve performance with 32-bit
microprocessors.
1) Pin 28 (B1) is used to enable/disable a pair of TAT? out-
puts, and pin 29 (BO on the DP8429) is a no connect.
When Bl is low, RASO and RAS1 are enabled such that
they both go low during an access. When B1 is high,
RAS2 and RASS are enabled. This feature is useful when
driving words of 32 bits or more since each m would
be driving only one half of the word. By distributing the
load on each m line in this way, the DP8428 will meet
the same AC specifications driving 2 banks of 32 DRAMs
each as the DP8429 does driving 4 banks of 16 bits each.
2) The hidden refresh function available on the DP8429 has
been disabled on the DP8428 in order to reduce the
amount of setup time necessary from g going low to
RASIN going low during an access of DRAM. This param-
eter, called tCSRU, is 5 ns for the DP8428 whereas it is
34 ns tor the DP8429. The hidden refresh function al-
lowed only a very small increase in system performance,
at microprocessor frequencies of 10 MHz and above.
Pin Definitions
Vco. GND, GND -- Vcc = 5V i10%. The three supply
pins have been assigned to the center of the package to
reduce voltage drops, both DC and AC. There are two
ground pins to reduce the low level noise. The second
ground pin is located two pins from Vcc, so that decoupling
capacitors can be inserted directly next to these pins. It is
important to adequately decouple this device, due to the
high switching currents that will occur when all 10 address
bits change in the same direction simultaneously. A recom-
mended solution would be a 1 pF multilayer ceramic capaci-
tor in parallel with a low-voltage tantalum capacitor, both
connected as close as possible to GND and Vcc to reduce
lead inductance. See Figure below.
‘MULTILAYEH
cmmc 'TANTALUM -
¢>——| |—<}
GND G-
TL/F/8649-8
'Capacitor values should be chosen depending on the particular application.
R0-R9: Row Address Inputs.
C0-C9: Column Address Inputs.
00-09: Multiplexed Address Outputs - This address is
selected from the Row Address Input Latch, the Column
Address Input Latch or the Refresh Counter.
RASIN: Row Address Strobe Input - RASIN directly con-
trols the selected RAS output when in an access mode and
all RAS outputs during hidden or external refresh.
8/5 (RFCK) - In the auto-modes this pin is the external
refresh clock input; one refresh cycle should be performed
each clock period. In the external access mode it is Row/
Column Select Input which enables either the row or column
address input latch onto the output bus.
CASIN (RGCK) - In the auto-modes this pin is the RAS
Generator Clock input. In external access mode it is the
Column Address Strobe input which controls CAS directly
once columns are enabled on the address outputs.
ADS: Address (Latch) Strobe Input - Row Address, Col-
umn Address, and Bank Select Latches are tall-through with
ADS high; latching occurs on high-to-low transition of ADS.
a: Chlp Select Input - When high, tTg disables all ac-
cesses. Refreshing, however, in both modes 0 and 1 is not
affected by this pin.
MO, M2 (RFSH): Mode Control Inputs - These pins select
one of the tour available operational modes of the DP8429
(see Table III).
Pin Definitions (Continued)
RFl/O: Refresh Input/Output - In the auto-modes this pin
is the Refresh Request Output. It goes low following RFCK
indicating that no hidden refresh was performed while RFCK
was high. When this pin is set low by an external gate the
on-chip refresh counter is reset to all zeroes.
WIN: Write Enable Input.
iw.. Write Enable Output - WE follows WIN unconditionally.
RAHS: Row Address Hold Time Select - Selects the
tRAH to be guaranteed by the DP8428 or DP8429 delay line
to allow for the use of fast or slow DRAMs.
trig.. Column Address Strobe Output - In mode 5 and in
mode 4 with CASIN low before R/E goes low, tts goes
low automatically after the column address is valid on the
address outputs. In mode 4 m follows CASIN directly af-
ter Fl/C goes low, allowing for nibble accessing. m is al-
ways high during refresh.
W 0-3: Row Address Strobe Outputs - The enabled
ms output (see Table II) follows RASIN directly during an
access. During refresh, all AW? outputs are enabled.
BO, BI: Bank Select Inputs - These pins are decoded to
enable one or two of the four FT/WS outputs during an access
(see Table I and Table II).
TABLE I. DP8429 Memory Bank Decode
Bank Select
(Strobed by ADS) Enabled RASn
0 0 RASO
0 1 RAS1
1 0 RAS?
1 1 RAS:,
TABLE II. DP8428 Memory Bank Decode
Bank Select
(Strobed by ADS) Enabled RASn
0 X R So & RAS1
1 X HAS? & RASa
Conditions for All Modes
INPUT ADDRESSING
The address block consists of a row-address latch, a col-
umn-address latch, and a resettable refresh counter. The
address latches are fall-through when ADS is high and latch
when ADS goes low. If the address bus contains valid ad-
dresses until after as goes low at the end of the memory
cycle, ADS can be permanently high. Otherwise ADS must
go low while the addresses are still valid.
DRIVE CAPABILITY
The DP8429 has timing parameters that are specified driv-
ing the typical capacitance (including traces) of 88, 5V-only
DRAMs. Since there are 4 TAS outputs, each is specified
driving one-fourth of the total memory. CK, WE and the
address outputs are specified driving all 88 DRAMs.
The graph in Figure 10 may be used to determine the slight
variations in timing parameters, due to loading conditions
other than 88 DRAMs.
Because of distributed trace capacitance and inductance
and DRAM input capacitance, current spikes can be creat-
ed, causing overshoots and undershoots at the DRAM in-
puts that can change the contents of the DRAMs or even
destroy them. To reduce these spikes, a damping resistor
(low inductance, carbon) should be inserted between the
DP8429 outputs and the DRAMs, as close as possible to
the DP8429. The damping resistor values may differ de,
pending on how heavily an output is loaded. These resistors
should be determined by the first prototypes (not wire-
wrapped due to the larger distributed capacitance and in-
ductance). Resistors should be chosen such that the tran-
sition on the control outputs is critically damped. Typical
values will be from 150 to 1000. with the lower values be-
ing used with the larger memory arrays. Note that AC pa-
rameters are specified with 150 damping resistors. For
more information see AN-305 "Precautions to Take When
Driving Memories".
DP8429 DRIVING ANY 256k or 1M DRAMS
The DP8429 can drive any 256k or 1M DRAMS. 256k
DRAMs require 18 of the DP8429's address inputs to select
one memory location within the DRAM. RAS-only refreshing
with the nine-bit refresh-counter on the DP8429 makes CAS
before RAS refreshing, available on 256k DRAMs, unneces-
sary (see Figure ta).
1 Mbit DRAMs require the use of all 10 of the DP8429 Ad-
dress Outputs (see Figure 1b).
READ, WRITE AND READ-MODIFY-WRITE CYCLES
The output signal, W. determines what type of memory
access cycle the memory will perform. If WI? is kept high
while cis goes low, a read cycle occurs. If WR; goes low
before m goes low, a write cycle occurs and data at DI
(DRAM input data) is written into the DRAM as tts goes
low. If W goes low later than tCWD after O_AS goes low, first
a read occurs and DO (DRAM output data) becomes valid,
then data DI is Written into the same address in the DRAM
as Te goes low. In this read-modify-write case, DI and DO
cannot be linked together. W always follows RF directly
to determine the type of access to be performed.
POWER-UP INITIALIZE
When Vcc is first applied to the DP8429, an initialize pulse
clears the refresh counter and the internal control flip-flops.
Mode Features Summary
4 modes of operation: 2 access and 2 refresh
II Automatic or external selected by the user
II Auto access modiprovides m. row to column
change, and then CAS automatically.
a Choice between two different values of tRAH in auto-ac-
cess mode
II CTA-S controlled independently in external control mode,
allowing for nibble mode accessing
a Automatic refreshing can make refreshes transparent to
the system
I tTAB' is inhibited during refresh cycles
DP8428/DP8429 Mode Descriptions
MODE O-EXTERNALLY CONTROLLED REFRESH
Figure 2 shows the Externally Controlled Refresh timing. In
this mode the refresh counter contents are multiplexed to
the address outputs. All Ris outputs are enabled to follow
RASIN so that the row address indicated by the refresh
counter is refreshed in all DRAM banks when RASIN goes
low. The refresh counter increments when RASIN goes
high. RFSH should be held low at least until RASIN goes
high (they may go high simultaneously) so that the refresh
address remains valid and all m outputs remain enabled
throughout the refresh.
A burst refresh may be performed by holding RFSH low and
toggling BASIN until all rows are refreshed. It may be useful
in this case to reset the refresh counter just prior to begin-
ning the refresh. The refresh counter resets to all zeroes
when RFI/O is pulled low by an external gate. The refresh
counter always counts to 511 before rolling over to zero. If
there are 128 or 256 rows being refreshed then O? or 08,
respectively, going high may be used as an end-of-burst
indicator.
In order that the refresh address is valid on the address
outputs prior to the Ris lines going low, RFSH must go low
before RASIN. The setup time required is given by tRFLRL in
the Switching Characteristics. This parameter may be ad-
justed using Figure 10 for loading conditions other than
those specified.
TABLE III. DP8428/DP8429 Mode Select Options
Mode Tl") M0 Mode of Operation
0 0 0 Externally Controlled
Refresh
1 0 1 Auto Refresh-Forced
4 1 0 Externally Controlled
Access
5 1 1 Auto Access
(Hidden Refresh)
DP8428/DP8429 Interface Between System and DRAM Banks
(5iT; _
ADDRESS
COLUMNS ;% omvsns
ADDRESS
>REFRESH
COUNTER
DP8429
'fhs----
COLUMN DECDDE
+ 5 ll 256 K
DYNAMIC
512 256K RAMS
moonmo 2:220
All 9 Bits of Refresh Counter Used
TL/F/8649-12
FIGURE 1a. DP8428/DP8429 with 256k DRAMs
COLU MNS ADDRESS
DRIVERS ADDRESS
REFRESH
COUNTER
DP8429
All 9 Bits of Refresh Counter Used
COLUMN DECODE
mooomc on
TL/F/8649-25
FIGURE 1b. DP8428/DP8429 with 1M DRAMS
DP8428/DP8429 Mode Descriptions (Continued)
CASIN AND n/C
lMSINL
F--- ‘RASINH -i-
C-- ttiFutt--;
OUTPUTS I l I ALL NTS‘: Low
ae n ---( - tRFPOLE// " 'nrmo
-trt-------1 / l l
ifs l, t. 3 ----1 larPoLu/ ~+i -tRFP0H0
-1 mount
nsrnssn cm REFRESH caum n X n +1 l coumzn RESET
OLD COLUMNS X
H lRFUJI
REFRESH COUNY n
lnmnv I ' -tcu--j
RF l/O
'lndicates Dynamic RAM Parameters
COUNTER RESET
TL/F/8649-13
FIGURE 2a. External Control Refresh Cycle (Mode 0)
man: XI mooeo X
-..... _ -
iirsrii
-/l-tmvl " F-mmm
'----0- ----_
tnmna _-- --.| l-tmoi:
air, n ( nu n+2 511 X ll x
FIGURE 2b. Burst Refresh Mode 0
Tb/F/8649-14
DP8428/DP8429 Mode Descriptions (Continued)
MODE I-AUTOMATIC FORCED REFRESH
In Mode 1 the R/C (RFCK) pin becomes RFCK (refresh
cycle clock) and the CASIN (RGCK) pin becomes RGCK
(R/VS generator clock). If RFCK is high and Mode 1 is en-
tered then the chip operates as if in MODE 0 (externally
controlled refresh), with all Rg-ts outputs following RASIN.
This feature of Mode 1 may be useful for those who want to
use Mode 5 (automatic access) with externally controlled
refresh. By holding RFCK permanently high one need only
toggle M2 (RFSH) to switch from Mode 5 to external re-
fresh. As with Mode 0, RFl/O may be pulled low by an ex-
ternal gate to reset the refresh counter.
When using Mode 1 as automatic refresh, RFCK must be an
input clock signal. One refresh should occur each period of
RFCK. If no refresh is performed while RFCK is high, then
when RFCK goes low RFI/O immediately goes low to indi-
cate that a refresh is requested. (RFI/O may still be used to
reset the refresh counter even though it is also used as a
refresh request pin, however, an open-collector gate should
be used to reset the counter in this case since RFI/O is
forced low internally for a request).
"1 F-icsro
After receiving the refresh request the system must allow a
forced refresh to take place while RFCK is low. External
logic can monitor RFRO (RFl/O) so that when RFRQ goes
low this logic will wait for the access currently in progress to
be completed before pulling M2 (RFSH) low to put the
DP8429 in mode 1. If no access is taking place when RFRO
occurs, then M2 may immediately go low. Once M2 is low,
the refresh counter contents appear at the address outputs
and R-A-S is generated to perform the refresh.
An external clock on RGCK is required to derive the refresh
KITS signals. On the second falling edge of RGCK after M2
is low, all ATR? lines go low. They remain low until two more
falling edges of RGCK. Thus FT/E remains high for one to
two periods of RGCK after M2 goes low, and stays low for
two periods. In order to obtain the minimum delay from M2
going low to Rt-xg going low, M2 should go low tRFSRG be-
fore the falling edge of RGCK.
The Refresh Request on RFI/O is terminated as ms goes
low. This signal may be used to end the refresh earlier than
it normally would as described above. If M2 is pulled high
pP NEXT CYCLE<
PROGRESSES
HISIN -]
uP CONTINUES
OPERATIONS
5ch --( T l--
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___..___
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© RFRQ goes low it no hidden refresh
occurred while RFCK was high
© Next AAVYN starts next access
© pP acknowledges refresh request
TL/F/8649-15
Forced refresh HAS starts after > T
(> lap)
Forced refresh HAS ends RFRQ
" removes refresh acknowledge
FIGURE 3. DP8428/DP8429 Performing a Forced Refresh (Mode 5 - 1 - 5) with Various Microprocessors
DP8428/DP8429 Mode Descriptions (Continued)
while the m lines are low, then the ITA-ss go high tRFRH
later. The designer must be careful, however, not to violate
the minimum Ats low time of the DRAMs. He must also
guarantee that the minimum A7g precharge time is not vio-
lated during a transition from mode 1 to mode 5 when an
access is desired immediately following a refresh.
If the processor tries to access memory while the DP8429 is
in mode 1, WAIT states should be inserted into the proces-
sor cycles until the DPB429 is back in mode 5 and the de-
sired access has been accomplished (see Figure 9).
Instead of using WAIT states to delay accesses when re-
freshing, HOLD states could be used as follows. RFRQ
could be connected to a HOLD or Bus Request input to the
system. When convenient, the system acknowledges the
HOLD or Bus Request by pulling M2 low. Using this
scheme. HOLD will end as the Th-s lines go low (RFI/O
goes high). Thus, there must be sufficient delay from the
time HOLD goes high to the DP8429 returning to mode 5, so
that the 5% low time of the DRAMs isn't violated as de-
scribed earlier (see Figure 3 for mode 1 refresh with Hold
states).
To perform a forced refresh the system will be inactive for
about four periods of RGCK. For a frequency of 10 MHz,
this is 400 ns. To refresh 128 rows every 2 ms an average of
'Resmtors required depends on DRAM load.
DHAMS Maybe 16k, 64k. 256k, 1M
For 4 Banks, can drive 16 data bits
f 6 Check Bits tor ECC.
For 2 Banks, can drive 32 data bits
+ 7 Check Bus for ECC.
For 1 Bank, can drive 64 data bits
f 8 Check Bits for ECC.
mm! m L---- Wt Pf 3
ALE )'-----it ADS MS ?
" ifs l
11mm.»
M 15.17.121.21 1
CIM, 7. l.9
mrut 1W5 r---"' mm
aow/cowun SEL F--"'-' mt tit
WIT? --- WTN
- m m no-o.7,n.o
M su T----' tt Ito
about one refresh per 16 ps is required. With a RFCK period
of 16 p5 and RGCK period of 100 ns, DRAM accesses are
delayed due to refresh only 2.5% of the time. It using the
Hidden Refresh available in mode 5 (refreshing with RFCK
high) this percentage will be even lower.
MODE 4 - EXTERNALLY CONTROLLED ACCESS
In this mode all control signal outputs can be controlled
directly by the corresponding control input. The enabled
R-AT; output follows RASIN, CM follows CASIN (with Fl/C
low), WE follows W and R/C determines whether the row
or the column inputs are enabled to the address outputs
(see Figure 4).
With Fl/C high, the row address latch contents are enabled
onto the address bus. am going low strobes the row ad-
dress into the DRAMs. After waiting to allow for sufficient
row-address hold time (tRAH) after m goes low, Fl/E can
go low to enable the column address latch contents onto
the address bus. When the column address is valid, O_AS
going low will strobe it into the DRAMs. W determines
whether the cycle is a read, write or read-modify-write ac-
cess. Refer to Figures 5a and 5b for typical Read and Write
timing using mode 4.
Page or Nibble mode may be performed by toggling CASIN
once the initial access has been completed. In the case of
page mode the column address must be changed before
M-lt, 7. B. 9
L, oo-r-L
on: K;,/ r/,S /,/ / P f ""' y 9/ Cr,
. ' s--- RAS E?
"t [- -+ ai; "l" "'/,/ '. I '
h. - /..
v C - wt y
w»a.7,a.s 6
1W, MRS. "m. 1M1
TL/F/B649-16
FIGURE 4. Typical Appllcation of DP8429 Using External Control Access and Refresh in Modes 0 and 4
DP8428/DP8429 Mode Descriptions (Continued)
MNTS -mmcms DYNAMIC MM
MS (ALE) Mammals
----tgtys--
'ASA tao-- -
5mm T //, T . ,,
ADDRESS/ "ie":yCe)( ADDRESS VALID " A. , f
BUS ,c- l " C '. _ f
---- I I I
nnsm I
I+IAsnL t
:%7fti l I I I
a/i) I I
uuwuvs
Ctts0.r?o «I Isnt- _-l I tiUOi- - l I I
u, IAPn _ Oro.)-- mo) - - I a Inca "
00-9 C ROWS VALID x COLUMNS VALID x HOW:
I >EIAsc‘I< orc. -3
'; - TCAS I * f"'"""-
- - mnc- - _ _
DRAM Mm our " DATA OUI VALID F--
TL/F/8649-17
FIGURE 5a. Read Cycle Timing (Mode 4)
INPUTS
-mmcn£s nvumc m
MS (ALE) mmmns
svsmn /
ADDRESS (ei. , annazss vmo
BUS /////
IT IN I
-asac-l
cnsm I
l [. - I
- ‘mn ,
m I I ( I I
_ I I I
own om m I f
ourPuIs I - mm "
- 1 I ' I
us 0.1.2.3 L, - 7 1tttt - _ I ttttX - ' I I I
--tgnt--_ tMit" - -ttt----l I I I - mI
T q "' " f
uo-s 737/53}? j; 3 news wtuo X coumus VALID X wws
I I "I 'cruu F-
cTs I.WLI l I -
TL/F/8649718
FIGURE 5b. Write Cycle Timing (Mode 4)
DP8428/DP8429 Mode Descriptions (Continued)
CASIN goes low to access a new memory location (see
Figure tic). Parameter tCPdit has been specified in order that
users may easily determine minimum tts pulse widths
when CASIN is toggling.
AUTOMATIC CAS GENERATION
CA-s is held high when 9/6 is high even if CASIN is low. If
CASIN is low when R/C goes low, cis goes low automati-
cally, tASC after the column address is valid. This feature
eliminates the need for an externally derived CASIN signal
to control m when performing a simple access (Figure 5a
demonstrates Auto-m generation in mode 4). Page or nib-
ble accessing may be performed as shown in Figure 5c
even if m is generated automatically for the initial access.
FASTEST MEMORY ACCESS
The fastest Mode 4 access is achieved by using the auto-
matic m feature and external delay line to generate the
required delay between RASIN and R/C. The amount of
delay required depends on the minimum tRAH of the DRAMs
being used. The DP8429 parameter tDIF1 has been speci-
fied in order that the delay between RASIN and RIC may be
minimized.
tDlFt = MAXIMUM (lRPDL - tRHA)
where ‘RPDL = 'TAS-IN to WM delay
and tFtHA = row address held from R/C going low.
The delay between A7stN and PVC that guarantees the
specified DRAM tRAH is given by
MINIMUM RASIN to PVC = tDlFl + tHAH.
Example
In an application using DRAMs that require a minimum tRAH
of 15 ns, the following demonstrates how the maximum
RASIN to CAS time is determined.
With tom (from Switching Characteristics) = 7 ns,
RASINto RIF) delay = 7 ns + 15 ns = 22 ns.
A delay line of 25 ns witl be sufficient.
With Auto-CAS generation, the maximum delay from R/C to
CAS (loaded with 600 pF) is 46 ns. Thus the maximum
RASIN to CAS time is 71 ns, under the given conditions.
With a maximum RASIN to Ris time (thDL) of 20 ns, the
maximum Ats to CM time is about 51 ns. Most DRAMs
with a 15 ns minimum tRAH have a maximum taco of about
60 ns, Thus memory accesses are likely to be R-AS" limited
instead of m limited. In other words, memory access time
is limited by DRAM performance, not controller perform-
REFRESHING IN CONJUNCTION WITH MODE 4
If using mode 4 to access memory, mode 0 (externally con-
trolled refresh) must be used for all refreshing.
MODE 5 - AUTOMATIC ACCESS WITH HIDDEN RE-
FRESHING CAPABILITY
Automatic-Access has two advantages over the externally
controlled access (mode 4). First, Ris, Ch% and the row to
column change are all derived internally from one input sig-
nal, RASlN. Thus the need for an external delay line (see
mode 4) is eliminated.
Secondly, since Ft/C and CASIN are not needed to gener-
ate the row to column change and m. these pins can be
used for the automatic refreshing function,
AUTOMATIC ACCESS CONTROL
Mode 5 of the DP8429 makes accessing Dynamic RAM
nearly as easy as accessing static RAM. Once row and col-
umn addresses are valid (latched on the DP8429 if neces-
sary), RASIN going low is all that is required to perform the
memory access.
U)tl \ 'r COLA
COL B COL C COL il
00-9 80W x
COLA X COLE X COLE x COL D
TL/F/8649-19
FIGURE 5c. Page or Nibble Access in Mode 4
DP8428/DP8429 Mode Descriptions (Continued)
l- -tMS -1
-1 IASA Lulu -
m - [AsnL : - _ IRICL --e
1 t F - ‘RICH”
,__._..._ _.___.___.\
anoaess INPUYS/ ADDRESS HUD t menu %
DMA _, um mm IF wan:
"'''''cr''-----''i,,,T,,",-c-"'
lam - - - l _ mm" l
MS 1 Witt' _ - '
l- - Im - ' -.. tMrr-- I
ROWS mmX COLUMNS VALID l
ttttht _ - _ Wu: - " -- IRCDH
------ttttDt-- -
-- -tt1S' ----
I READ ,
WE I _ I
F------, - -mttTE-------l
‘- twcs' t' [
- ttytt' - i, ton” >1
mm (mm)! VALID mun)
---- - Inn? - ,fi.‘
'lndicates Dynamic RAM Parameters
TL/F/8649-20
FIGURE 6. Mode 5 Timing
(Refer to Figure 6) In mode 5 the selected m follows
RASIN immediately, as in mode 4, to strobe the row address
into the DRAMs. The row address remains valid on the
DP8429 address outputs long enough to meet the tRAH re-
quirement of the DRAMs (pin 4, RAHS, of the DP8429 al-
lows the user two choices of tRAH). Next, the column ad-
dress replaces the row address on the address outputs and
CWC; goes low to strobe the columns into the DRAMs. W
determines whether a read, write or read-modify-write is
The diagram below illustrates mode 5 automatic control sig-
nal generation.
ttAsm y-, - m
mg" - (IOM)
use - W;
TL/F/8649-21
REFRESHING IN CONJUNCTION WITH MODE 5
When using mode 5 to perform memory accesses, refresh-
ing may be accomplished:
(a) externally (in mode 0 or mode l)
(b) by a combination of mode 5 (hidden refresh) and
mode 1 (auto-refresh)
or (c) by a combination of mode 5 and mode 0
(a) Externally Controlled Refreshing in Mode 0 or Mode 1
All refreshing may be accomplished using external refresh-
es in either mode 0 or mode 1 with R/C (RFCK) tied high
(see mode 0 and mode 1 descriptions). If this is desired, the
system determines when a refresh will be performed, puts
the DP8429 in the appropriate mode, and controls the R/VS
signals directly with RASIN. The on-chip refresh counter is
enabled to the address outputs of the DP8429 when the
refresh mode is entered, and increments when RASIN goes
high at the completion of the refresh.
(b) Mode 5 Refreshing (hidden) with Mode 1 refreshing
(auto)
(Refer to Figure Za) It RFCK is tied to a clock (see mode 1
description), RFI/O becomes a refresh request output and
goes low following RFCK going low it no refresh occurred
while RFCK was high. Refreshes may be performed in
mode 5 when the DP8429 is not selected for access (E is
high) and RFCK is high. If these conditions exist the refresh
counter contents appear on the DP8429 address outputs
and all m lines follow RASIN so that if RASIN goes low
(an access other than through the DP8429 occurs), all 'TAS
lines go low to perform the refresh. The DP8429 allows only
one refresh of this type for each period of RFCK, since
RFCK should be fast enough such that one refresh per peri-
od is sufficient to meet the DRAM refresh requirement.
DP8428/DP8429 Mode Descriptions (Continued)
Once it is started, a hidden refresh will continue even if
RFCK goes low. However, a must be high throughout the
refresh (until RASIN goes high).
These hidden refreshes are valuable in that they do not
delay accesses. When determining the duty cycle of RFCK,
the high time should be maximized in order to maximize the
probability of hidden refreshes. it a hidden refresh doesn't
happen, then a refresh request will occur on RFl/O when
RFCK goes low. After receiving the request, the system
must perform a refresh while RFCK is low. This may be
done by going to mode 1 and allowing an automatic refresh
(see mode 1 description). This refresh must be completed
while RFCK is low, thus the RFCK low time is determined by
the worst-case time required by the system to respond to a
refresh request.
(c) Mode 5 Refresh (Hidden Refresh) with mode 0 Refresh
(External Refresh)
This refresh scheme is identical to that in (b) except that
after receiving a refresh request, mode 0 is entered to do
the refresh (see mode 0 description). The refresh request is
terminated (RFl/O goes high) as soon as mode 0 is en-
tered. This method requires more control than using mode 1
(auto-refresh), however, it may be desirable if the mode 1
refresh time is considered to be excessive.
Example
Figure 7b demonstrates how a system designer would use
the DP8429 in mode 5 based on certain characteristics of
his system.
System Characteristics:
1) DRAM used has min tHAH requirement of 15 ns and
min IASR of 0 ns
2) DRAM address is valid from time TV to the end of the
memory cycle
3) four banks of twenty-two 256k memory chips each are
being driven
Using the DP8429 (see Figure 7b):
1) Tie pin 4 (RAHS) high to guarantee a 15 ns minimum
tRAH which is sufficient for the DRAMs being used
2) Generate RASIN no earlier than time TV + tASRL (see
switching characteristics), so that the row address is
valid on the DRAM address inputs before RAS occurs
3) Tie ADS high since latching the DRAM address on the
DP8429 is not necessary
4) Connect the first 20 system address bits to RO-RS and
C0-C9, and bits 21 and 22 to BO and B1
5) Connect each RAS output of the DP8429 to the RAS
inputs of the DRAMs of one bank of the memory array;
connect 00-09 of the DP8429 to A0-A9 of all DRAMs;
connect CAS of the DP8429 to CAS of all the DRAMs
Figure i? illustrates a similar example using the DP8428 to
drive two 32-bit banks.
' chxL
FORCES REFRESH
tRFtit
‘HFCKH l
N0 FORCED
HIDDEN REFRESH ALLOWED REFRESH
PROCESSOR ACCESSING ELSEWHERE
c3 / /
i PROCESSOR CYCLE TIME - l-- I
iijitTg l I
Icsiin - F--
Jl2 t mnneu nsrnssu ALREADY
i 1 - ---- PERFORMED. no suasauusm
REFRESH ALLOWED in ms cvcu
/ nuns 1
lim MODE 5 NQ none 5
- -- tarrnns
Ianan l--
rm ll. K -
3 l on: MS -
I--- SELECTED
2Trts _-l
,;,,';,/ l " 44/
note 4225/17, ///1/ (ri/fx arm n x Mills X COLS (,er)(" nows
cTs I l
TL/F/8649-22
FIGURE 7a. Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing
DP8428/DP8429 Mode Descriptions (Continued)
SYSTEM CLOCK
//". //
mruv 'txt
mass" cwcx
i'irftFtt
1mtTii
TL/F/86d9-23
FIGURE 7b. Typical Application ot DP8429 Using Modes 5 and 1
Applications
If one desires a memory interface containing the DP8429
that minimizes the number of external components required,
modes 5 and 1 should be used. These two modes provide:
1) Automatic access to memory (in mode 5 only one signal,
RASIN, is required in order to access memory)
2) Hidden refresh capability (refreshes are performed auto-
matically while in mode 5 when-non-local accesses are
taking place, as determined by CS)
3) Refresh request capability (if no hidden refresh took
place while RFCK was high, a refresh request is generat-
ed at the RFI/O pin when RFCK goes high)
4) Automatic forced refresh (If a refresh request is generat-
ed while in mode 5, as described above, external logic
should switch the DP8429 into mode 1 to do an automat-
ic forced refresh. No other external control signals need
be issued. WAIT states can be inserted into the proces-
sor machine cycles it the system tries to access memory
while the DP8429 is in mode 1 doing a forced refresh).
Some items to be considered when integrating the DP8429
into a system design are:
1) The system designer should ensure that a DRAM access
not be in progress when a refresh mode is entered. Simi-
larly, one should not attempt to start an access while a
refresh is in progress. The parameter tRFHRL specifies
the minimum time from RFSH high to RASIN going low to
initiate an access.
2) One should always guarantee that the DP8429 is enabled
for access prior to initiating the access (see Icsnu).
3) One should bring RASIN low even during non-local ac-
cess cycles when in mode 5 in order to maximize the
chance of a hidden refresh occurring.
4) At lower frequencies (under 10 Mhz), it becomes increas-
ingly important to differentiate between READ and
WRITE cycles. RASIN generation during READ cycles
can take place as soon as one knows that a processor
READ access cycle has started. WRITE cycles, on the
other hand, cannot start until one knows that the data to
be written at the DRAM inputs will be valid a setup time
before m (column address strobe) goes true at the
DRAM inputs. Therefore, in general, READ cycles can be
initiated earlier than WRITE cycles.
5) Many times it is possible to only add WAIT states during
READ cycles and have no WAIT states during WRITE
cycles. This is because it generally takes less time to
write data into memory than to read data from memory.
Applications (Continued)
SYSTEM CLDCK'
INPUT W; '
REFRESH CLOCKI
ge-ries-y I
JZ-BIT DATA IUS
1Whir-15 E75 MTA 6-31
DATA tl- 15 DATA l6-31
TL/F/8649-24
FIGURE 7c. Typical Application of DP8428 Using Modes 5 and 1
The DP84XX2 family of inexpensive preprogrammed medi-
um Programmable Array Logic devices (PALS) have been
developed to provide an easy interface between various mi-
croprocessors and the DP84XX family of DRAM controller/
drivers. These PALs interface to all the necessary control
signals of the particular processor and the DP8429. The
PAL controls the operation of the DP8429 in modes 5 and l,
while meeting all the critical timing considerations discussed
above. The refresh clock, RFCK, may be divided down from
the processor clock using an IC counter such as the
DM74LS393 or the DP84300 programmable refresh timer.
The DP84300 can provide RFCK periods ranging from 15.4
us to 15.6 p.s based on an input clock of 2 to 10 MHz.
Figure 8 shows a general block diagram for a system using
the DP8429 in modes 1 and 5. Figure 9 shows possible
timing diagrams for such a system (using WAIT to prohibit
access when refreshing). Although the DP84XX2 PALs are
offered as standard peripheral devices for the DP84XX
DRAM controller/drivers, the programming equations for
these devices are provided so the user may make minor
modifications for unique system requirements.
ADVANTAGES DF DP8429 OVER
A DISCRETE DYNAMIC RAM CONTROLLER
1) The DP8429 system solution takes up much less board
space because everything is on one chip (latches, re-
fresh counter, control logic, multiplexers, drivers, and in-
ternal delay lines).
2) Less effort is needed to design a memory system. The
DP8429 has automatic modes (1 and 5) which require a
minimum of external control logic. Also programmable ar-
ray logic devices (PALS) have been designed which allow
an easy interface to most popular microprocessors (Mo-
torola 68000 family, National Semiconductor 32032 fami-
Iy, Intel 8086 family, and the Zilog 28000 family).
3) Less skew in memory timing parameters because all crit-
ical components are on one chip (many discrete drivers
specify a minimum on-chip skew under worst-case condi-
tions, but this cannot be used if more then one driver is
needed, such as would be the case in driving a large
dynamic RAM array).
4) Our switching characteristics give the designer the critical
timing specifications based on TTL output levels (low ---
0.8V, high = 2.4V) at a specified load capacitance. All
timing parameters are specified on the DP8429:
A) driving 88 DRAM's over a temperature range of 0-70
degrees centigrade (no extra drivers are needed).
B) under worst-case driving conditions with all outputs
switching simultaneously (most discrete drivers on the
market specify worst-case conditions with only one
output switching at a time; this is not a true worst-case
condition!).
Applications (Continued)
\B-BIT MICROPROCESSOR DATA 1lus
" RAMS MAY M wt Mk -
t MICROPIOEESSOR ADDRESS nus m iso) I4
um 006 RAM Annnzss aus_ M.8 _
norm no.5.7 5.9 G."; ' 75 9
cns.7.a.9 r-r-ig' ------
ADDRESS BI WE
uscoum _ m
I I I M r'--''
nnna no.6 ,
amass ' AOS 7,5.9
- m 'rm-
Is sus . wr
MICROPROCESSOR omauo FIFO 'm
is 093423 flASt I _ A
CLOCK 2-10MH1 1 nncx AO 6. ,
n/W . wm 'asa oi. I s 9 ,
upwsn am 'UT, _ m
LOWER am LI , wt m L
- _ I-I
WN swus nmm _ " 6 -
CM 7.3.9
- "l 1 . LOWER
r 1 JiM - am
RASIN W ' VT
ITHESELKT wmmwr urn M? M0
T0 ms DPEIXXZ Cum 0 ie-AT ll
INSERTS A WAIT STATE I f A.‘
ouamc ACCESSING
THIS MAt BE NECESSARY l
row vsnv FAST MICRO " BM
PROCESSORS ETsu SELECI umn am "S244
k-"-- DEL SELECI LOWER am
urnzssnnv Ir INSIMIETus muons
amwnmns ummwcsr us: 5 umecm
“WM ammo m MHS usczssnv T MORE mm on: "o--
TL/F/8649-26
FIGURE 8. Connecting the DP8429 Between the 16-bit Microprocessor and Memory
mum roucso I---
I--- 4rrsEs'r--1 -l REFlttti4
nccsss
lmmoxv "us-l-res,.?,..?,?" -/ I-- nsuonv our-j--- menu" oc---!
nmaoo mums: Low mu m
arc! to cums mmuzmc mac: or
/ NIDBEN REFIESM
cl snzcmn /
EtSEWKEIIE /
-o----' ,
" , I l
/ / TH
\. [ W
mus oumns JT',
mouwuvs SEL‘D ALL SElD'D ALL \ SEL‘D
\ in mm mm: uoms
l w nww
_ ----q-.--
V ' . TL/F/8649-27
'T Is microprocessor's clock period
FIGURE 9. DP8429 Auto Refresh, Access with WAIT States
Switching Characteristics
All A. C. parameters are specified with the equivalent load
capacitances, including traces, of 88 DRAMs organized as 4
banks of 22 DRAMs each. Maximums are based on worst-
case conditions including all outputs switching simulta-
neously, This, in many cases, results in the AC valves
shown in the DP84XX DRAM controller data sheet being
much looser than true worst case maximum AC dalays. The
system designer should estimate the DP8429 load in his/
her application, and modify the appropriate A. C. parame-
ters using the graph in Figure " Two example calculations
are provided below.
+150 j
-500 -300 -100 0+100 +300 +500
TL/F/8649-28
FIGURE 10. Change In Propagation Delay
relative to "true" (application) load minus
AC specitled data sheet load
Examples
1) A mode 4 user driving 2 banks of DRAM has the follow-
ing loading conditions:
CAS - 300 pF
00-09 - 250 pF
RAS _ 150 pF
A.C. parameters should be adjusted in accordance with Fig-
ure 70 and the specifications given for the 88 DRAM load as
follows:
max 1RPDL = 20 ns - 0 ns = 20 ns (since RAS load-
ing is the same as that which is spec'ed)
max thDL = 32 ns - 7 ns = 25 ns
max tCCAS = 46 ns - 7 ns = 39 ns
maxtRCC = 41 ns - 6 ns = 35 ns
min tRHA is not significantly effected since it does not
involve an output transition
Other parameters are adjusted in a similar manner.
2) A mode 5 user driving one bank of DRAM has the
following loading conditions:
as - 120 pF
OO-OS) - 100 pF
AM - 120 pF
A. C. parameters should be adjusted as follows:
with RAHS = "I'',
maxthL = 70 ns - 11 ns = 59 ns
maxtRCDL = 55 ns +1ns -- 11 ns = 45 ns
(the + 1 ns is dty_Lt_o lighter A7tG loading; the - 11 ns
is due to lighter CAS loading)
mintRAH = 15 ns +1ns :16ns
The additional 1 ns is due to the fact that the FT/CS line
is driving less (switching faster) than the load to which
the 15 ns spec applies. The row address will remain
valid for about the same time irregardless of address
loading since it is considered to be not valid at the
beginning of its transition.
nutrm Ito
uunsn TEST POINT
TEST 159
TL/F/8649-29
FIGURE 11. Output Load Circuit
Absolute Maximum Ratings (Note1)
Operating Conditions
Specifications for Military/Aerospace products are not Mln Max Units
contained In this datasheet. Refer to the associated Vcc Supply Voltage 4.50 5.50 V
reliability electrlcal test specifications document. TA Ambient
Supply Voltage, Vcc 7.0V Temperature 0 + 70 T _
Storage Temperature Range -65'C to + 150''C
Input Voltage 5.5V
Output Current 150 mA
Lead Temp. (Soldering, 10 seconds) 300°C
Electrical Characteristics Vcc = 5.0V i 10%, 0°C s TA s 70''C unless otherwise noted (Note 2)
Symbol Parameter Conditions Min Typ Max Units
Vc InputClamp Voltage Vcc = Min, k: = - 12 mA - 0.8 - 1.2 V
IIH Input High Current for all Inputs Vm = 2.5V 2.0 100 )LA
I) RSI Output Load Current for RFl/O VIN = 0.5V, Output high -0.7 - 1.5 mA
ML] Input Low Current for all Inputs" VIN = 0.5V -0.02 -0.25 mA
I” ADS, WCCS, M2, A7glN VIN ' 0.5V -0.05 -0.5 mA
Ihr. Input Low Threshold 0.8 V
VIH Input High Threshold 2.0 V
V0L1 Output Low Voltage' 'OL = 20 mA 0.3 0.5 V
VOL2 Output Low Voltage for RFI/O 'OL = 8 mA 0.3 0.5 V
VOH1 Output High Voltage' IOH = - 1 mA 2.4 3.5 V
VOH2 Output High Voltage for RFI/O IOH = - 100 HA 2.4 3.5 V
I10 Output High Drive Current' VOUT = 0.8V (Note 3) -50 - 200 mA
IOD Output Low Drive Current' VOUT = 2.4V (Note 3) 50 200 mA
ICC Supply Current VCC = Max 150 240 mA
'Excepl RFl/O
"Except RFl/O, ADS, RIC, ' M2, AMIN
Switching Characteristics: DP8428 and DP8429
Vcc = 5.0V , 10%, 0°C 3 TA g 70°C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
. These values are 00-09, CL = 500 pF; RAS0-RAS3, G. = 150 pF; W, CL = 500 pF; CAS, CL = 600 pF; RL = soon
unless otherwise noted. See Figure " for test load. Maximum propagation delays are specified with all outputs
switching.
. . Preliminary
t t a =
Symbol Access Parameter Condition CL All CL 50 pF Units
Mln Max Min Max
thLo RASW to CAS Low Delay Figure 6 57 97 42 85 ns
(RAHS = 0) DP8428-80/29-80
thLo RASIN to UAS Low Delay Figure 6 57 87 42 75 ns
(RAHS = 0) DP8428-70/29-70
talc” RASIN to CAS Low Delay Figure 6 48 80 35 68 ns
(RAHS = 1) DP8428-80/29-80
tRICU RASIN to CAS Low Delay Figure 6 48 70 35 58 ns
(RAHS = 1) DP8428-70/29-70
thH RASIN to CAS High Delay Figure 6 37 ns
tRCDLo RA-sto C-AT; Low Delay Figure6' . ---- 43 / 80) ns
(RAHS = 0) DP8428-80/29-80. -
tRCDLo RAS to CAS Low Delay Figure g _ I 43 72 __..) ns
(RAHS = O) DP8428-70/29-70f --"
Switching Characteristics: DP8428 and DP8429 (Continued)
VCC = 5.0V i 10%, 0°C 3 TA s 70°C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
. These values are 00-09, CL = 500 pF; RASO-RAS3, CL = 150 pF; Wit?, CL = 500 pF; CAS, th. = 600 pF; RL = 5000
unless otherwise noted. See Figure " for test load. Maximum propagation delays are specified with all outputs
switching.
.. Preliminary
Symbol Access Parameter Condition CL "All Cc = 50 pF Unlts
Min Max Min Max
tRCDL1 RAS to CA§ Low Delay Figure 6 34 63 ns
(RAHS = 1) DP8428-80/29-80
IRCDU RAS to CAS Low Delay Figure 6 34 55 ns
(RAHS = 1) DP8428-70/29-70
tRCDH RAS to CAS High Delay Figure 6 22 ns
tRAHO Row Address Hold Time Figure 6 25 25 ns
(RAHS = 0, Mode 5)
tRAm Row Address Hold Time Figure 6 15 15 ns
(RAHS = l, Mode 5)
IASC Column Address Set-up Time Figure 6 0 0 ns
(Mode 5)
move RASIN to Column Address Figure 6 94 ns
Valid (RAHS = 0. Mode 5) DP8428-80/29-80
tRcvo R-AgiN to Column Address Figure 6 85 ns
Valid (HAHS = O, Mode 5) DP8428-70/29-70
tRCV1 RASIN to Column Address Figure 6 76 ns
Valid (RAHS = 1, Mode 5) DP8428-80/29-80
tRCV1 RASIN to Column Address Figure 6 68 ns
Valid (RAHS = 1, Mode 5) DP8428-70/29-70
tRpDL RASIN to ATe Low Delay Figures tia, 5b, 6 21 18 ns
tHPDH RASIN to RAS High Delay Figures 5a, 5b, 6 20 17 ns
IASRL Address Set-up to RASIN low Figures 5a, 5b, 6 13 ns
tAPD Address Input to Output Figures 5a, 5b, 6 36 25 ns
tSPD Address Strobe High to Figures 5a, tit; 48 ns
Address Output Valid
tASA Address Set-up Time to ADS Figures 5a, 5b, 6 5 ns
tAHA Address Hold Time from ADS Figures 5a, 5b, 6 10 ns
tADS Address Strobe Pulse Width Figures 5a, 5b, 6 26 ns
twpD WIN to W? Output Delay Figure tit, 28 ns
tCPDL CAgN to CAS Low Delay Figure tit; 21 32 ns
(R/C low, Mode 4)
tCPDH CAS_IN to GAS High Delay Figure Sb 16 33 ns
(R/C low, Mode 4)
tCPdit tCPDL - tCPDH See Mode 4 1 1 ns
Description
IRCC Column Select to Column Figure 5a 41 ns
Address Valid
tRCR Row Select to Row Figures 5a, tit, 45 ns
Address Valid
tRHA Row Address Held from Figure 5a 7 ns
Column Select
tCCAs RIC Low to CA6 Low Delay Figure 5a 50 ns
(CASIN Low, Mode 4) DP8428-80/29-80
tCCAS H/C Low to CM Low Delay Figure 5a 46 ns
(CASIN Low, Mode 4) DP8428-70/29-70
tDIF1 Maximum (tRpDL - 1RHA) See Mode 4 7 ns
Description
tara Maximum (tHcc - tCPDL) 13 ns
Switching Characteristics: DP8428 and DP8429 (Continued)
Vcc -- 5.0V i 10%, ty'C C TA s 70°C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
' These values are 00-09, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, th. = 500 pF; CAS, CL = 600 pF; RL 2 500n
unless otherwise noted. See Figure " for test load. Maximum propagation delays are specified with all outputs
switching.
Symbol Refresh Parameter Condition CL All CL = 50 pF Units
Min Max Min Max
tRc Refresh Cycle Period Figure 2a 100 ns
tRASINL,H Pulse Width of RASIN Figure 2a 50 ns
during Refresh
1RFPDL0 RASIN to RAS Low Delay Figure Pa 28 ns
during Refresh (Mode 0)
tRFPDL5 RASIN to RAS Low Delay Figure 7 38 ns
during Hidden Refresh
tRFpDHo RASIN to RAS High Delay Figure 2a 35 ns
during Refresh (Mode 0)
tRFPDH5 RASIN to RAS High Delay Figure 7 44 ns
during Hidden Refresh
tRFLCT RFSH Low to Counter Figures Pa, 3 38 ns
Address Valid c-s = X
tRpLRL RFSH Low Set-up to RASIN Figure 2a 12 ns
Low (Mode O), to get
Minimum 1ASR ' 0
tRFHRL RFSH High Setup to Access Figure 3 25 ns
RASIN Low
1RFHRV RFSH High to Row Figure 3 43 ns
Address Valid
tROHNC RAS High to New Count Figure 2a 42 ns
tRST Counter Reset Pulse Width Figure 2a 46 ns
ton RFI/O Low to Counter Figure Pa 80 ns
Outputs All Low
‘RFCKLH Minimum Pulse Width Figure 7 100 ns
of RFCK
T Period of RAS Generator Figure 3 30 ns
tRGCKL Minimum Pulse Width Low Figure 3 15 ns
of RGCK
tRGCKH Minimum Pulse Width High Figure 3 15 ns
of RGCK
trmat. RFCK Low to Forced RFRQ Figure 3 66 ns
(RFI/O) Low CL = 50 pF
RL = 35k
tFRQH RGCK Low to Forced RFHQ Figure 3 55 ns
High CL = 50 pF
RL = 35k
Switching Characteristics: DP8428 and DP8429 (Continued)
VCC = 5.0V , 10%, 0°C 2 TA f, 70°C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMs, including trace capacitance.
' These values are 00-09, CL = 500 pF; RASO-RAS3, CL = 150 pF; W, CL = 500 pF; CAS, CL = 600 pF; RL = 500tt
unless otherwise noted. See Figure " for test load. Maximum propagation delays are specified with all outputs
switching.
Symbol Refresh Parameter Condition CL All th. = 50 pF Units
Min Max Min Max
tgGRL RGCK Low to RAS Low Figure 3 21 41 ns
tRGRH RGCK Low to RAS High Figure 3 23 48 ns
tRQHRF RFSH Hold Time from RGCK Figure 3 2T ns
tRFRH RFSH High to RAS High (See Mode 1 42 ns
(Ending Forced Refresh Description)
early)
tHFSRG RFSH Low Set-up to (See Mode 1 12 ns
RGCK Low (Mode 1) Description)
Figure 3
tCSHH a High to RASIN Low for Figure 7 10 ns
Hidden Refresh
tCSRU CC; Low to Access RASIN Figure 3 34 ns
for DP8429 Low (Using Mode 5 with
Auto Refresh Mode)
tCSRL1 a Low to Access RASIN Figure 3 5 ns
for DP8428 Low (Using Mode 5 with
Auto Refresh Mode)
tCSRLO t% Low to Access RASIN (See Mode 5 5 ns
Low (Using Modes 4 or 5 Description)
with externally controlled
Refresh)
tRKRL RFCK High to RASIN 50 ns
low for hidden Refresh
Input Capacitance TA = 25°C (Note 2)
Symbol Parameter Condition Min Typ Max Units
CIN Input Capacitance ADS, R/C, CS, M2, RASIN 8 pF
CIN Input Capacitance All Other Inputs 5 pF
Note 1: "Absolute Mammum Ralungs" are the values beyond which me safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these Ilmlls The table ot "Electrical Characteristics" provides conditions for actual devrce operation.
Note 2: All typical values are for TA " 25''C and Vcc = 50V.
Note 3: Ttus test Is provided as a monitor of Drlver output source and sink current capability. Caution should be exerCIsed m testing this parameter. In testing these
parameters, a 15tt vesrstor should be placed m senes with each output under test. One output should be tested at a time and test time should not exceed 1 second.
Note 4: Input pulse 0V to 3 ov. IR - t; = 25 ns. t: 2.5 MHz, tew = 200 ns. Input reference Pont on AC measurements IS ISV Output reference points are 2.4V for
High and 0.8V for Low
Note 5: The load capacnance on RF I/O should not exceed 50 pF.
Physical Dimensions inches (millimeters)
0125 tt_ttm-0Ji6tt L r--/la-'ih--C
iran (01:24:21; ihtttt-$t0tt _I l
mu (1 19.4130;
II tm- I 055
_ t (0189 - , 397)
“1"”: KANE Y" "P
[015 - 0 Nil
[13“ - 0.5“)
ct ,2 g- ,4 CL....
(12.45)
0.” - 0.015 mm
" mm 4.331: mm)
m an m l IV an
1590-0520 mm:
mm-us 15)
Hermetic DuaHn-Llne Package (D)
Order Number DP84280-7o or DP8428D-80; or
DP8429D-70 or DP84290-80
NS Package Number D52A
DP8428/NS32828, DP8429/NS32829
1 Megabit High Speed Dynamic RAM Controller/Drivers
Physical Dimensions inches (millimeters) (Continued)
0350:0300
(1170:2032]
ICSPRCES AT
I' I l I I I I I
Irlmi 0.050=0.500
(20.96) (1170:2032)
MOM " SHOES IT
(8.382)
BIA NOM
PEDES'ML
Plastic Chip Carrier (V)
Order Number DP8428V-70 or DP8428V-80; or
(c.5031 -
MIN " +10“
0101-0113 “‘4 (1.143)
(2.5424391) t
n _ , / A
i 11.045
(1.1 '
e-e-rr-e-"'-'-:";
tM13-0.0t8 " 0.950 T
(0.3304457) -
Ji'',',")'.' m REFS"
’sams’ Ii88L-.0.ir5
comer (25.02-25.211
nmsusnon scum
IhW6--lr.t13t
(tMti0-ih813)
to3t-thtU0
(u.n1:-1.n151“1
'.165-0nil0
0.1105 41.015 (1.1914512)
iirirfmiiir"
P68A (REV m
75/?3/
DP8429V-70 or DP8429v-80
NS Package Number V68A
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Datasheets for electronic components.
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This file is the datasheet for the following electronic components:
DP8428D-70 - product/dp8428d-70?HQS=T|-nu|I-nulI-dscataIog-df-pf-null-wwe
DP8428D-80 - product/dp8428d-80?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
DP8428V-70 - product/dp8428v—70?HQS=T|—nu|I—nulI-dscatalog-df-pf-nulI-wwe
DP8428V-80 - product/dp8428v—80?HQS=T|—nu|I—nulI-dscatang-df-pf-nulI-wwe
DP8429D-70 - product/dp8429d-70?HQS=T|-nu|I-nulI-dscataIog-df-pf-null-wwe
DP8429D-80 - product/dp8429d-80?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
DP8429V-70 - product/dp8429v—70?HQS=T|—nu|I—nulI-dscatalog-df-pf-nulI-wwe
DP8429V-80 - product/dp8429v—80?HQS=T|—nu|I—nulI-dscatang-df-pf-nulI-wwe
