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DP8431V-33-DP8432V-33
microCMOS Programmable 256K/1M/4M Dynamic RAM Controller/Drivers
TL/F/11118
DP8430V/31V/32V-33
microCMOS
Programmable
256k/1M/4M
Dynamic
RAM
Controller/Drivers
July 1993
DP8430V/31V/32V-33 microCMOS Programmable
256k/1M/4M Dynamic RAM Controller/Drivers
General Description
The DP8430V/31V/32V dynamic RAM controllers providea
low cost, single chip interface between dynamic RAMand
all8-,16-and 32-bit systems.The DP8430V/31V/32V gen-
erateall the required access control signal timingfor
DRAMs.An on-chip refresh request clockis usedto auto-
matically refreshthe DRAM array. Refreshesand accesses
are arbitratedon chip.If necessary,a WAITor DTACKout-
put inserts wait statesinto system access cycles, including
burst mode accesses. RASlow time during refreshesand
RAS precharge time after refreshesand backto backac-
cessesare guaranteed throughthe insertionofwait states.
Separate on-chip precharge countersfor each RAS output
canbe usedfor memory interleavingto avoid delayed back back accesses becauseof precharge.An additionalfea-
tureofthe DP8432Vis two access portsto simplify dual
accessing. Arbitration among these ports and refreshis
doneon chip.
FeaturesOn chip high precision delaylineto guarantee critical
DRAM access timing parameters microCMOS processforlow power High capacitance driversfor RAS, CAS,WE and DRAM
addresson chipOn chip supportfor nibble, page and static column
DRAMs Byte enable signalson chip allow byte writingina word
sizeupto32bits withno external logic Canusea single clock source.Upto33 MHz operating
frequencyOn board Port A/PortB (DP8432V only)/refresh arbitra-
tion logic Direct interfacetoall major microprocessors4 RASand4 CAS drivers(the RAS and CAS configura-
tionis programmable)
Ýof Pins Ýof Address Largest Direct Drive Access
Control (PLCC) Outputs DRAM Memory Ports
Possible Capacity Available
DP8430V 68 9 256kbit 4Mbytes Single AccessPort
DP8431V 68 10 1 Mbit 16Mbytes Single AccessPort
DP8432V 84 11 4 Mbit 64Mbytes Dual AccessPorts(A andB)
Block Diagram
DP8430V/31V/32V DRAM Controller
TL/F/11118–1
FIGURE1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
StaggeredRefreshTM isatrademark ofNationalSemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
