DP8470N ,Floppy Disk Support Chip Data Separator & Write PrecompensationPin Descriptions
MP Pln PCC Pin
Symbol No. No. Function
NRZ READ DATA 1 1 This output will ..
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DS90CF584MTD ,LVDS 24-Bit Color Flat Panel Display (FPD) LinkFeaturesn 20 to 65 MHz shift clk supportThe DS90CF583 transmitter converts 28 bits of CMOS/TTLdata ..
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DS90CP04TLQX ,4x4 Low Power 2.5 Gb/s LVDS Digital Cross-Point SwitchBlock Diagrams20028701 2004 National Semiconductor Corporation DS200287 Functional
DP8470N
Floppy Disk Support Chip Data Separator & Write Precompensation
Natiqnal " oc, ' 1, ~/ W6 PRELIMINARY
1iemicor?.rhmtw // Vs» - c, _ e April1986
Corporation
DP8470 Floppy Disk Support Chip
Data Separator & Write Precompensation
General Description
This part is a general purpose data separator which can be
used to generate a read clock for FM or MFM encoded
data. This read clock can be used with many existing floppy
format rather than MFM encoded. Also, the controller needs
to know when a valid address mark has been read from the
data stream. This disk support chip does both of these func-
disk controllers including the pPD765A, 8272A, and tions.
WDI 79x. It can also be used with National Semiconductor's
Hard Disk Controller, DP8466, tor a combination hard disk/ Features
floppy disk system. The data separator can be used for data " Analog dual-gain PLL data separator
rates ranging from 125 kbits/sec up to 1.25 Mbits/sec. I: Write precompensati on (0-393 ns)
This part also contains a write precompensation circuit. Nor- n Requires no external trimmable components
mally a disk cohtroller will determine whether a bit of data a Supports FM/MFM 125 kbits-1.25 Mbits/sec
needs to be shifted early, late, or not at all. The controller I: Interface t II o la fl di k t ll
does not do the actual shifting however. This disk support o a p pu r opby tS con m ers.
chip will do the actual shifting that is requested by the con- 11 Interface to DP8466 hard disk controller
- Address Mark Found output
troller.
- NRZ output
enable this part to be interlaced to a hard disk controller
. . . . I
A few other miscellaneous Circwts have been me uded to u Pump up / do t ut for testing
such as the DP8466. The hard disk controller requires that n Pw.po r CMOS .
the data read off from the disk be converted to an NRZ " M-pin narro C age or 28-pin PCG
Block Diagram
UP/DOWN
C ' SECONDARY
LH PLL
"tt cm
R ATE LINE COMPARATOR PUMP
PREAMBLE
DEECT DIVIDER
READ GATE CONTROL (PROGRAMMABLE)
Fu/uru AMP
TL/F/8593-t
gr c)---;
'Tiy(e/2
TRLSTATEo IS a registered trademark at National Somiconauctov Com
©1986 Nauonal Sgmticort6uetor Corporation TL/F/8593 l RRD-B20M46fpritttttd in U. S. A,
uonesuedwoeeid 9mm :3 JOIBJEdes emu dguo uoddns xsia AddoH ougda
Connection Diagram
DuaI-ln-Line Package
Plastic Chip Carrier
V m g ' 's
NR2 READ om - 1 24 - vcc g 8 g o
0 u o E '
AUFe2 23 -READMODE g E , g g
EARLY PRECOMP - 3 22 - WRITE DATA OUT E E u. pl: to a tl
, a E E 9' n: g
LATE PRE00UP- 4 21 --POMi' UP/DOWN
WRITE DATA lN - s 20 w-PREcthtP o
Fu/um - 6 19 - PRECOMP 1 NC -PIM' ay DOWN
READ cm- 7 18 -PRECOMP 2 NC -PRECOMP 0
READ DATA OUT- a 17 -READ DATA IN WM DATA N "N0
READ CLOCK- 9 16 - DATA RATE 0 ru/ Mru -PttEC0UP 1
oscz - 10 15 - PUMP CURRENT REM) GATt ‘PRECOW’ 2
Ot/cut- 11 14 -i)ATA RATE 1 READ 0hTh 00T -REAO DATA m
(mi) - 12 13 - FILTER READ CLOCK -DATA RATE 0
TL/F/8593-2 s = g c: ‘2; - 'E
Top View 8 3 tdt g E it'
G ttt 3
s ' c2
TL/F/8593-9
Top View
Note: Make no corrections to NC pins (No connection).
Pin Descriptions
MP Pln PCC Pin
Symbol No. No. Function
NHZ READ DATA 1 1 This output will present data read from the disk in NRZ format based on the read clock.
This output is set to a high impedance state when Read Gate is not asserted.
AMF 2 2 This output could be used with any controller that needs an indication of a valid address
mark. This pin goes high for one bit period when an address mark is detected. This
output is set to a high impedance state when Read Gate is not asserted.
EARLY/PRECOMP 3 3 These two active-high inputs determine whether the incoming write-data pulse should
LATE/PRECOMP 4 4 be shifted early or late in time.
WRITE DATA IN 5 7 Active-high data input from the disk controller.
FM/MFM 6 8 0 = FM, 1 = MFM. This pin also affects the data rate.
READ GATE 7 9 While this input is low, the PLL will lock to its center frequency. While this input is high,
the PLL will lock to signal on the Read Data In pin.
READ DATA OUT 8 10 Athive-high data output to the floppy controller. The Read Data Out is synchronized to
the Read Clock Output.
READ CLOCK 9 1 1 This is a clock output that has the same frequency as the data rate. This output is
always derived from the output of the VCO. While reading data, the VCO is tracking the
data rate. When not reading data, the VCO is locked to its reference frequency.
OSC 1,2 10,11 12,13 These two pins enable the connection of a crystal to form the reference oscillator.
Optionally an external clock can be used instead. The clock would drive Osc 1 while
Osc 2 would be left open.
FILTER 13 15 This pin is the output of the duaI-gain charge pump and is also the input to the VCO. A
simple filter is attached to this pin.
DATA RATE 0 16 19 These two pins select the data rate that this chip will sync to:
DATA RATE 1 14 17 00 = 125FM/250MFM
01 = 250FM/500MFM
10 = 500FM/1000MFM
11 = Test Mode
PUMP CURRENT 15 18 A resistor is attached to this pin to set the charge pump current.
Pin Descriptions (Continued)
DIP Pln PCC Pin
Symbol No. No. Function
READ DATA IN 17 20 Active-high data input from the disk drive.
PRECOMP O 20 24 These three input pins select the amount of write precompensation.
PRECOMP 1 19 22
PRECOMP 2 18 21
PUMP UP/DOWN 21 25 This active-high output is the logical OR of Pump Up and Pump Down. This is used for
diagnostic purposes.
WRITE DATA OUT 22 26 Active-high data output to the floppy drive. This is the same data as is input on the
Write Data In pin, except it has been write-precompensated and delayed.
READ MODE 23 27 This input determines what read algorithm is used to select between the low and the
high gain mode. (Low = 4-state algorithm, high = 2-state algorithm.)
V00 24 28 These pins are the power supply pins for both the digital circuitry and the analog
GROUND 12 14 circuitry.
Typical Floppy Disk Drive Application
PROCESSOR
- RESET
MOTOR ON
DIRECTION
LOW CURRENT
HEAD SELECT
TRACK O DRWE
WRITE PROTECT
SEEK COMPLETE
WRITE GATE
CONTROLLER
RO GATE
RD DATA -
RD CLK
- Rt) t)ATA-
- Wit DATA-
WR DATA -
DP847O
ADDRESS
DECODE
.-'iiiit
Fu/Mru -
PRECOMP SET
DATA RATE
READ MODE
SEPARATOR
PRECOMP
CURRENT SET
-"()('-CL
-r1LTER
47 pF =
-r-ll-l"
'=' BNHZ
11,3114»
TL/F/8593-3
Functional Description
The data separator consists of a dual gain analog PLL
(Phase Locked Loop). This PLL synchronizes a VCO (Volt-
age Controlled Oscillator) to the raw data signal read from a
disk drive. The Read Clock pin is derived from the VCO. The
Read Data Out pin mirrors the Read Data In pin except that
it is centered with respect to the Read Clock. In addition,
NRZ encoded data is available at the Read Clock. In addi-
tion, NRZ encoded data is available at the NRZ Read Data
The PLL consists of three main components, a phase com-
parator, a filter, and a voltage controlled oscillator (VCO), as
shown in the Block Diagram. The basic operation of a PLL is
fairly straightforward. The phase comparator detects the dif-
terence between the phase of the VCO output and the
phase of the raw data being read from the disk. This phase
difference is converted to a current which either charges or
discharges a filter. The resulting voltage of the filter chang-
es the frequency of the VCO in an attempt to reduce the
phase difference between the two signals. A PLL is
"locked" when the frequency of the VCO is exactly the
same as the average frequency of the read data. This is
somewhat of a simplified view because it ignores such
topics as loop stability, acquisition time, and filter values.
The external filter simply consists of two capacitors and a
resistor as shown in the typical application diagram. Another
resistor is used to set the charge pump current.
The quarter period delay line is used to determine the cen-
ter of a bit cell. It is important that this delay line be as
accurate as possible. A typical data separator would nor-
mally require an external trim to adjust the delay. An exter-
nal trim is not required for the DP8472/74 however. A sec-
ondary PLL is used to automatically calibrate the delay line.
The secondary PLL also calibrates the center frequency of
the VCO.
The Preamble Detect circuit is used with the tour-state algo-
rithm to determine when the PLL switches from the high
gain mode to its low gain mode. This circuit scans the in.
coming data for the frequency corresponding to a preamble
plus or minus 15 percent.
Circuit Operation
READ MODE
There are two read modes to choose from. The Read Mode
is selected with the Read Mode pin. The state of this pin
should not change during an actual read operation.
Two-State Diagram
IDLE MODE
HIGH GAIN
REFERENCE
RDG.ATE RDGATE
DATA MODE
LOW GAIN
RDGATE
Data _ first incoming pulse received. TL/FN593-4
MODE ONE (TWO-STATE DIAGRAM)
When Read Gate is not asserted, the PLL is locked to the
crystal frequency in its high-gain mode with a phase/tre-
quency comparator. When Read Gate is asserted, the PLL
will remain locked to the crystal until the first data bit arrives.
It will then lock to the incoming data in its low-gain mode
with a phase-only comparator. It will stay in this mode until
Read Gate is deasserted.
The NR? Data Output will remain low until 8 bits have been
read. This is to guarantee that the clock pulses from the
preamble have become stable. The Read Data Out is en-
abled as soon as the first data bit arrives.
Four-State Diagram
IDLE MODE
HIGH GAIN
H IGH GAIN
PRE DETB
RDGATE
RDGATE . PREDEH 6
PREDETI 6
RDGATE
PREDET 16
DATA MODE
LOW GAIN
RDGATE
PreDete = 8 consecutive hits ot preamble frequency. TL/F/8593-5
PreDet16 = 16 consecutive bits of preamble frequency.
MODE TWO (FOUR-STATE DIAGRAM)
When Read Gate is not asserted, the PLL is locked to the
crystal frequency in its high-gain mode with a phase/tre-
quency comparator. When Read Gate is asserted, a pream-
ble-detect circuit is enabled. This circuit looks for consecu-
tive bits of the correct preamble frequency. The PLL will
stay locked to the crystal frequency until 8 consecutive pre-
amble bits are read. At this point the PLL will lock on to the
incoming data (preamble) in its high-gain mode with a
phase-only comparator. When the preamble-detect circuit
finds 16 consecutive bits of the preamble frequency, the
Data Output and the NRZ Data Output logic will be enabled.
If at any time before the 16 bits are counted the preamble-
detect circuit goes false, the PLL will return to the Idle Mode
locked to the crystal. As soon as the preambIe-detect circuit
goes false after the 16 bits are counted (such as when be-
ginning of the address mark is read) the PLL will switch to its
low-gain mode. It will stay in this mode until Read Gate is
deasserted. The timing is such that the comparison of the
first bit of the Address Mark is done in the low-gain mode.
Between the time in which Read Gate is asserted and the
Read Data Output is enabled (states 1 and 2 of the 4-state
diagram), the data pattern 4E(hex) or FF(hex) will be output
Circuit Operation (Continued)
for MFM and FM respectively on the Read Data Output pin.
The NR2 Data Output will remain low during this time.
WRITE MODE
When writing data, the rising edge of the signal presented to
the Write Data Input is delayed before it appears on the
Write Data Output. The number of delays is shown in Table l.
The actual value of the delay is determined by the PreComp
Set pins. There is also a base delay as specified in the AC
timing characteristics.
TABLE I
Early Late ' of Delays
1 1 illegal
Design Considerations
The operating characteristics of this part are totally pin pro-
grammable. The designer needs to set three parameters by
tying pins either high or low. These three parameters are the
data rate, the amount of write precompensation, and the
read mode algorithm.
DATA RATE, FM/MFM
The data rate is determined by three pins (Data Rate 0,
Data Rate 1, FM/MFM) and also the clock frequency. The
normal clock frequency is 8 MHz. The selectable data rates
based on an 8 MHz clock are shown in Table II. If a data
rate is needed that is not shown in the 8 MHz column, it may
be produced by varying the clock frequency. See the AC
Electrical Characteristics for the acceptable range of clock
frequencies.
If either of these parameters (data rate or FM/MFM) are
subject to change then these pins could be connected to
switches, an output port, or through some logic from the
controller's drive select output.
The test mode is used by National for testing purposes. It
should not normally be used for anything else.
WRITE PRECOMPENSATION
Another parameter to set is the amount of write preCompen-
sation needed for the disk drive being used. This value is
generally specified by the drive manufacturer. The amount
of precompensation used is based on the Precomp Set pins
and the Data Rate as shown in Table Ill.
If the amount of write precompensation is subject to
change, then these pins could be connected to switches, an
output port, or through some logic from the controller's drive
select output.
It is sometimes desirable to enable write precompensation
tor the inner tracks of a disk only. Some controllers have an
output signal that indicates when the head is over a track
that needs write precompensation. The easiest way to im-
plement this signal is to choose the amount of write pre-
compensation needed, look up in the table which pins need
to be tied high and which need to be tied low. Connect the
low pins to ground. Connect the high pins to the controller's
write precompensation enable output pin.
CRYSTAL
Normally an 8 MHz crystal is attached in parallel across the
two oscillator pins. There should also be a separate 47 pF
capacitor attached to each pin with the other side of each
capacitor attached to ground. If the system already has an
8 MHz source, this may be used to drive the Osc 1 pin while
leaving the Osc 2 pin floating. The frequency at this pin is
used to set the center frequency of the VCO and the initial
delay of the quarter period delay line. It is also used for the
write precompensation circuit timing. See the AC Electrical
Characteristics for the acceptable range of the crystal. Vary-
ing the frequency will affect many operating parameters as
specified in the appropriate sections.
TABLE II
Data Rate FM/ Actual Data Rate Actual Data Rate FILTER
1 0 MFM (t = 8 MHz) (Variable f) The filter is used for the main PLL. The values recommend-
0 0 125 kbits/sec t/64 ed for the two resistors and the capacitor are given in Table
8 0 1 250 kbits/sec f/32 N based on the data rate needed, If more than one data
0 1 0 250 kbits/sec f/32 rate will be used, there are two alternatives. The values can
0 1 1 500 kbits/sec the be used that are shown in the table for the multiple data
1 o o 500 kbits/sec f/16 rates. These values are a trade off of PLL characteristics
1 0 1 1.00 Mbits/sec t/8 that are not ideal for either data rate. Another alternative is
1 1 0 test mode to actually have two separate filters with the capability of
1 1 1 test mode switching in one or the other either with a manual switch or
t = clock frequency. an analog switch which can be software controlled.
TABLE III
Precomp Set Amount ot Preeornpensatlon
2 1 0 Data Rt = 00 Data m = 01 Data Rt = 10
t = 8 MHz Variable' f = 8 MHz Variable f t = 8 MHz Varlablef
0 0 0 0 ns 0X 0 ns 0X 0 ns 0X
0 0 1 107 ns 3X 36 ns 1X 36 ns 1X
0 1 0 143 ns 4X 71 ns 2X 71 ns 2X
0 1 1 179 ns 5X 107 ns 3X 107 ns 3X
1 0 0 214 ns 6X 143 ns 4X 143 ns 4X
1 o 1 250 ns 7X 179 ns 5X 179 ns 5X
1 1 0 321 ns 9X 214 ns 6X illegal
1 1 1 393 ns 11X 250 ns 7X illegal
X = 2/7t ns. wheret ' clock frequency.
TABLE IV
Data Rate R1 R2 CI C2
125 kbits/sec FM kn n nF HF
250 kbits/sec FM kit n nF piF
500 kbits/sec FM kn n nF pF
250 kbits/sec MFM 10.0 kn 100 n 4.7 nF 0.047 HF
500 kbits/sec MFM kn n nF uF
l Mbit/sec MFM kn n nF pF
1.25 Mbits/sec MFM kn n nF p.F
125 FM/250 MFM kbits/sec kn n nF pF
250 FM/500 MFM kbits/sec kn n nF p.F
500 FM/ 1000 MFM kbits/sec kn n nF M'
Interfacing
DISK DRIVE INTERFACE
The connection between the Support Chip and the Disk
Drive is very simple. The disk drive's Write Data line con-
nects to the support chip's Write Data Out pin. The disk
drive's Read Data line connects to the support chip's Read
Data In pin.
FLOPPY CONTROLLER
Simply connect the Write Data and Read Data pins of the
controller to the Write Data In and Read Data Out pins of
the Support Chip. Connect the Early and Late Precomp out-
puts from the controller to the Early and Late Precomp in-
puts of the disk support chip.
The Read Gate input pin of the disk support chip must be
connected to the pin ot the controller that indicates when
the controller is trying to read valid data. On the uPD765A,
8272A this is the VCO pin. On the WD179x this is the VFOE
The Read Clock output pin of the disk support chip must be
connected to the pin ot the controller that requires a data
window (or data clock). This is a window that defines wheth-
er an MFM encoded pulse is a data pulse or a clock pulse.
The polarity of this pulse is indeterminant. On the pPD765A,
8272A this is the DW pin. On the WDI 79x this is the RCLK
HARD DISK CONTROLLER
This floppy support chip has been designed to interface di-
rectly to the DP8466 Hard Disk Controller. Connect the
Write Data lines exactly the same way as for the floppy
controller. Connect the Write Precomp lines the same way
The hard disk's Read Data line should be connected to the
support chip's Read Data In pin. Also, the controller's Read
Gate output is connected to the Read Gate input of the
support chip. The controller does not use the support chip's
Read Data Out pin. The controller needs the data read from
the disk to be in NRZ format rather than MFM encoded
format. Simply connect the NR? Read Data pin of the sup-
port chip to the Read Data pin of the controller. Connect the
Read Clock output of the support chip to the Read Clock
input of the controller.
The Address Mark Found output of the support chip gets
connected to the Address Mark Found input of the control-
Note: It write precornpensation is used as well as AMF with the DP8466, the
signal to indicate eany precomp and the signal to indicate AMF must
be multiplexed by the Write Gate output at the controller since the
DP8466 combines these two functions on the same pin.
PLL Performance
The information in this section is not needed to use this part.
It is included for completeness. The performance of the PLL
is determined from the following factors:
KVCO - Change in the frequency of the VCO due to a volt.
age change at the VCO input.
ch0 = 10 MRad/s/volt.
lcp - Charge pump current. Set by the external resistor
R1 across the reference voltage set by the chip.
lcp = 1.2 V/R1. This current can be set anywhere
between 50 FA and 350 " While in the high gain
mode, the current is doubled.
C2 - Filter capacitor.
R2 - Filter resistor. Determines the PLL damping factor.
c, - This filter capacitor improves the performance of
the PLL although it has only a secondary effect.
Using second order PLL formulas (Le. ignoring the effect of
C1) the filter components can be chosen to obtain the re-
quired performance.
The bit jitter tolerance of the PLL is given by,
ton = (cho/QN x Icp/thr X 1/02)“2
where N is the number of VCO cycles between two phase
comparisons (N = 2 during the preamble).
The acquisition time (time to lock to the correct phase and
frequency) is given by,
to, Ct'. 6/ ton.
The trade off, when choosing filter components, is between
acquisition time while the PLL is locking and jitter immunity
while reading data.
The damping factor is given by,
t--- (on A (R2 JK C2)/2
and is usually set at about 0.7.
Functional Waveform
Read Data Tlmlng
READ DATA IN n
VCO "iflfLrlfU1fLrlfflfLrLrLrLrlflffl.n
READ om OUT n n
m cut "L.r"ulTLlTLjTLlTL.lTLlTLlTLr"rLr1
NRI' |__] [“1 I""|
AMF . I"""""'"-]
TL/F/8593-6
. = It Read Clock starts out of phase.
Absolute Maximum Ratings Operating Conditions
Specificatlons tor Mllltary/Aerospace products are not Min Max Unlts
contalned In this datasheet. Refer to the associated Supply Voltage NCC) 4.5 5.5 V
rellablllty electrlcal test ttpete-lotus document. DC Input or Output Voltage 0 Vcc V
Supply Voltage (Vcc) -0.5 to + 7.0V Operating Temperature Range (T A): 0 + 70 "C
DC Input Voltage (Vm) - 1.5 to Vcc + 1.5V
DC Output Voltage (VOUT) _ 0.5 to VCC + 0.5V
Clamp Diode Current $20 mA
DC Electrical Characteristics Vcc = 5V 110% unless otherwise specified
Symbol Parameter Condltlons TA = tt'C to +70°C Unlts
VIH Minimum High Level
Input Voltage 2.0 V
" Maximum ow Leve 0.8 V
Input Voltage
VOH Minimum High Level Out VIN = VIH or "
- 3.7 V
“OUTI - 2 mA
VOL Maximum Low Level Out VIN = V'H or VIL
llourl = 2 mA
Im Maximum Input m Vcc or GND i1.0 HA
Current
. - s =
loz Maximum TRI STATE VOUT Vcc or GND t 10.0 “A
Leakage Current
'00 Maximum VIN = Vcc or GND 3.0 mA
Supply Current FIN = 8 MHz
ICC Maximum VIN = 2.4V or 0.5V
Supply Current FIN = 8 Mhz 20.0 mA
AC Electrical Characteristics Vcc = 5V i10%. C = 150 pF, unless otherwise specified
TA = trtt to 70°C
Symbol Parameter f = 8 MHz , = variable Unlts
Min Max Mln Max
f Crystal Frequency 4 10 MHz
DR Data Rate 125 1250 Kbit/s
READ TIMING
tugs Data Rate Setup to Depends on
Data In Filter Used
tRMS Read Mode Setup to
Read Gate 100 ns
tFMS FM/MFM Setup to Depends on
Data In Filter Used
4 M 1 09
tags Read Gate Setup to 600 100 + ns
Data In
tDRH Data Rate Hold 2 Bit
from Read Gate Windows
tRMH Read Mode Hold 2 Bit
from Read Gate Windows
AC Electrical Characteristics Vcc = 5V i10%, C -- 150 pF, unless otherwise specified (Continued)
TA = tr'C to 70°C
Symbol Parameter t == 8 MHz f = variable Unlts
Min Max Min Max
READ TIMING (Continued)
tFMH FM/MFM Hold 2 Bit
from Read Gate Windows
tRGH Last Data In to 2 Bit
Read Gate Disable Windows
tnGF Read Gate Off Time
between Heads 600 ns
tRDO Read Data Offset
from Center of 34 ns
Read Clock
tNRZ NR2 & AMF Data
Offset from Read 20 ns
Clock Edge
th Pulse Width of 50 ns
Data In
tom Pulse Width of 8.8 x 108 1.6 M 109
Data Out 1 10 200 f f ns
WRITE TIMING
tans Data Rate Setup to
Write Data In 5 ns
tpss Precomp. Setup to
Write Data In 125 ns
tags Read Gate Setup to 4 x 109
Write Data In 600 100 + ns
tps Early/ Late Setup to - 160 ns
Write Data In (Note 1)
tpn Early/ Late Hold from
Write Data In 200 ns
tDRWH Data Rate Hold from
Write Data In 1.0 p.s
IPSH Precomp. Hold from
Write Data In Hs
IRGH Read Gate Hold from
Write Data In 1.0 “8
twl Write In Pulse
Width 20 ns
. 1.76 It 109 2.8 y:109
two Wnte Out Pulse 220 350 ns
Width f f
tlo Write In to 280 Typ. 30 + 2 X 109 ns
Write Out (Early Precomp.) f
ewp Pr of i 10 %
Write Precomp.
Note 1: The Early and Late pins do not need to be valid until 160 ns after the rising edge of the write data in signal. This is to accommodate interfacing to the
IAPD765A.
PLL Characteristics
Symbol Parameter Value
K¢High Phase Comparator & Charge Pump 5 VREF T
Gain Constant. High Gain Mode. (Note I) 2arR yp.
VREF Voltage at Set Pump Current Pin 1.2V Typ.
Km“, Low Gain Mode (Note 1) 2.5 VREF Typ
27TH .
cho Gain of VCO (Note 2) 5/ N MRad/S/V Typ.
tvco Center Frequency of VCO f/ 2 Typ.
tyrrER Maximum Tolerance of Bit Jitter (Note 3) (0.95) Typ
4 x DR .
tPOWER ON Time from Full Vcc Power to
Guaranteed Functionality 50 ms Max
Note 1: R - pump cunent set resistor (8k-20k).
Note 2: N = ' of V00 cycles per bit.
Note 3: DR = Data Rate.
Timing Diagrams
DAIA RATE
READ MODE
ru/uru
DATA IN
DAM OUT
wzaacaxor-L.._,w'"=-"
DATA RATE
PRECOMP SET
READ GATE
EARLY/LATE
WRITE IN
WRITE OUT
Read Timlng
Write Timing
TL/F/8593-7
TL/F/B593-8
Physical Dimensions inches(millimeters)
- ox--------------]
(0.635) 11.10 (02 77)
_E51 WWWWE Jnlmm IISI Filliil
0.315 MAX 0.295
(0.001) GLASS (1.403)
LtJlAll2lulLUtAlLLllAlLutL0lL12lt1-2j "s's,_g.t.r1e.-e.r.,ti.ir,.
(0. 762- 1.397)
RAD TVP
cuss 0.060 10.005 mu» L. 0290-0320
SEALANT (1.524 20.127) IPL-tu-tll (LT-uz?)
l I'"""")
MM S 0225
(4.572) (5.715)
MAX MAX
~—rT tum8-0.0tt
"' ei'' --.---
30° M'' 4/ (02N-tl.305l
TYP‘ TYP
M95 /yallfh., I 0.100 :0__0_10‘! L 0.010 20003 tt,":-".si-':c,-s,e-ursr-,', (2-3:) L Il.31ll-iMt0 "
(2 Tu) ENDS (2. " W254) triiia.TriE 457 to. Wye?) MIN (MN-ttMt)
J24F(REV G)
Molded Dual-ln-Llne Package (J)
Order Number DP8470J
NS Package Number J24F
1.N3-1.2N
/ 0002 (31.57-3t.tti)
tt (2.331)
(2 PLS)
PIN NO. 1 h 0250x0005
'im"),; ' a.mu-tiirfr)
J' , i
' 11L]L3JILT5 MIL] I UTEHHHJLI
0171100 t 0002 5.150100 nus
0.3in-tl.3N (1.575) OPTIONAL
(1.52-0120) m
11-0“) 0130:0005
'hit,)--; (- |J,302i0.127) 4L
i _" I l !lcll?i11gyg--ygg, 200
[-iiiiil5)b"iii-"l'fii'i (350:- 5000)
0.009-0.015 1
(irihT--triir1)" Hi I
(r6lil) l tMN-tMM
th 01a+0 000 (3.1N-3.556l
0325 +1040 . 0075:0015 - L J rss-h-e-i-r',:,-,)--)--
-tl.0t5 - Mm "305 $0381) (t7.TsriWes7 05710 070) MIN
(rtss Ho“) 0.100 :0010 8tP Ir' m
4391 (2.5020254)
Dual-ln-Llne Package (N)
Order Number DP8470N
NS Package Number N24
NZAC [REV F]
DP8470 Floppy Disk Support Chip Data Separator & Write Precompensation
Physical Dimensions inches (millimeters) (Continued)
(1.14:)
" x45.
UAW -il.430
(10.“ - 10.92)
SQUARE
(CONTACT DIIENSION)
0120 0.013 -0.0"
"32-0.tu0 715m) - (0.3304151) 0.05-on
(om- um) mu m- um 4.572)
rr' - l
T,T,,,t7,,f- -
(0.171 4.31) i j l l
Alt No.1 tMN-ttmt tlntr4-lh118
mm _" ' (0.K0-il.M3y tui-tsa-r;
0150 "P
(11.43) -
as; so
am 4.4a
(ttab-ttar,
AilME VIM (REV GI
Plastic Chip Carrier (V)
Order Number DP8470V
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
I. Life support devices or systems are devices or 2. A critical component is any component ot a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
% mm Wot mm: Semiconducuw us Japan Ltd. .. " '
corporation 0mm! 4.403 Ikobukuvo. Hong Kong Ltd. Do m Lula. (Amtrak) PTY, Ltd.
2900 Setnitxmductor Drive Wttsttmdstntsso 193495 Toshima-ku. South“! m Mm Av. Brig. Fant Lima, 830 21/3 High Street
PO. Box 58090 0-8000 Muncnen 21 Tokyo 171. lean Austin Tm. 4th F100! 8 Andy Blyswatu. Victoria 3153
Santa Cam, CA 950528090 West Germany Tor (03) 988-2181 22-26A Austin Avenue 01452 Sao Paulo. SP. Basal Australia
Tel: (we) 721-5000 Tel: (089) 5 70 95 01 FAX: 011-81‘3-986-1700 Tsimsrmsui. Komaon. H.K. Tot: (55/11) 212-5066 Tel: (03] 729-6333
TWX: (910) 339-9240 Telex: 522772 Tel: 34231290, Fr243645 Tthttx:391-t13t931 NSBR BR Telex: M32098
(table: NSSEAMKTG
TB'OII 52996 NSSEA HX
National does not Issume any reptmsitWtt tot use 01 any circuitry dosa'ibod. no circuil patent licenses are Impued Ind Nanonal reserves the right II any time mthml whee to chanon sud mummy and 'ptro'tWations,
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DP8470 - product/dp8470?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
DP8470J - product/dp8470j?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
DP8470N - product/dp8470n?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
DP8470V - product/dp8470v?HQS=TI-nulI—nu|I-dscatalog-df-pf-nulI-wwe
