DS1005H-75 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1005M-100 , 5-Tap Silicon Delay Line
DS1005M-125 ,5-Tap Silicon Delay LineELECTRICAL CHARACTERISTICS (0°C to 70°C; V = 5.0V ± 5%)CCPARAMETER SYM TEST MIN TYP MAX UNITS NOTES ..
DS1005M-150 , 5-Tap Silicon Delay Line
DS1005M-150+ ,5-Tap Silicon Delay LinePIN DESCRIPTIONTAP 1-TAP 5 - TAP Output NumberV - +5 VoltsCCGND - GroundNC - No ConnectionIN - Inpu ..
DS1005M-200 ,5-Tap Silicon Delay LineDS10055-Tap Silicon Delay Linewww.dalsemi.com
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DS1005H-60-DS1005H-75-DS1005M-125-DS1005M-150+-DS1005M-200-DS1005S-125-DS1005S-60-DS1005S-75
5-Tap Silicon Delay Line
FEATURESAll-silicon time delay5 taps equally spacedDelay tolerance ±2 ns or ±3%, whichever isgreaterStable and precise over temperature and
voltage rangeLeading and trailing edge accuracyEconomicalAuto-insertable, low profileStandard 14-pin DIP, 8-pin DIP, or 16-pin
SOICTape and reel available for surface-mountLow-power CMOSTTL/CMOS compatibleVapor phase, IR and wave solderabilityCustom delays availableQuick turn prototypesExtended temperature range available
PIN ASSIGNMENT
PIN DESCRIPTIONTAP 1-TAP 5- TAP Output Number
VCC- +5 Volts
GND- Ground- No Connection- Input
DESCRIPTIONThe DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns
to 250 ns, with an accuracy of ±2 ns or ±3%, whichever is greater. This device is offered in a standard 14-
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology isachieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
DS1005
5-Tap Silicon Delay LineTAP 2
TAP 4
GND
TAP 5
TAP 3
TAP 1
VCC
DS1005 14-Pin DIP (300-mil)See Mech. Drawings Section
TAP 2
TAP 4
GND
VCC
TAP 1
TAP 3
TAP 5
DS1005M 8-Pin DIP (300-mil)
DS1005S 16-Pin SOIC
(300-mil)
TAP 2
TAP 4
GND
TAP 5
TAP 3
TAP 1
VCC
DS1005
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1Custom delays available
DS1005
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-1.0V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-55°C to +125°C
Soldering Temperature260°C for 10 secondsShort Circuit Output Current50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 5.0V ± 5%)
AC ELECTRICAL CHARACTERISTICS(TA = 25°C; VCC = 5V ± 5%)
CAPACITANCE(TA = 25°C)
DS1005
NOTES:1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns or ±3%, whichever
is greater.
4. See Test Conditions.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of ±1.5 ns or
±4%, whichever is greater.
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows
down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of theinput pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of theinput pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the inputpulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the inputpulse and the 1.5V point on the trailing edge of any tap output pulse.
DS1005
TEST SETUP DESCRIPTIONFigure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:Ambient Temperature25°C ±=3°C
Supply Voltage (VCC)5.0V ±=0.1V
Input PulseHigh = 3.0V ±=0.1V
Low = 0.0V ±=0.1V
Source Impedance50 ohm maximum
Rise and Fall Time3.0 ns maximumPulse Width500 ns
Period1 μs
OUTPUT:Each output is loaded with the equivalent of a 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
DS1005
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 3
