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DS1249Y-70IND ,2048k Nonvolatile SRAM19-5631; Rev 11/10 DS1249Y/AB 2048k Nonvolatile SRAM
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DS1249AB-70IND-DS1249Y-70IND
2048k Nonvolatile SRAM
FEATURES 10 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Unlimited write cycles Low-power CMOS operation Read and write access times of 70 ns Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time Full ± 10% VCC operating range (DS1249Y) Optional ± 5% VCC operating range
(DS1249AB) Optional industrial temperature range of
-40°C to +85°C, designated IND JEDEC standard 32-pin DIP package
PIN ASSIGNMENT
PIN DESCRIPTION A0 - A17 - Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+5V)
GND - Ground
NC - No Connect
DESCRIPTION The DS1249 2048k Nonvolatile SRAMs are 2,097,152-bit, fully static, nonvolatile SRAMs organized as
262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1249Y/AB
2048k Nonvolatile SRAM 19-5631; Rev 11/10
13
10
11
12
14
31
32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED A14A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20 A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
DS1249Y/AB
READ MODE The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs
(A0 - A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either tCO for or tOE for OE rather than tACC.
WRITE MODE The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The DS1249AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1249Y provides full-functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protects themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1249AB and 4.5 volts for the
DS1249Y.
FRESHNESS SEAL Each DS1249 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is
enabled for battery backup operation.
DS1249Y/AB
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperature Range -40°C to +85°C
Lead Temperature (soldering, 10s) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES DS1249AB Power Supply Voltage VCC 4.75 5.0 5.25 V
DS1249Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1249AB) (TA: See Note 10) (VCC = 5V ±10% for DS1249Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -2.0 +2.0 µA
I/O Leakage Current CE ≥ VIH ≤ VCC IIO -2.0 +2.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE=2.2V ICCS1 1.0 1.5 mA
Standby Current CE=VCC-0.5V ICCS2 100 150 µA
Operating Current ICCO1 85 mA
Write Protection Voltage (DS1249AB) VTP 4.50 4.62 4.75 V
Write Protection Voltage (DS1249Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 10 20 pF
Input/Output Capacitance CI/O 10 20 pF
DS1249Y/AB
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1249AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1249Y)
PARAMETER SYMBOL
DS1249AB-70
DS1249Y-70 UNITS NOTES
MIN MAX Read Cycle Time tRC 70 ns
Access Time tACC 70 ns to Output Valid tOE 35 ns to Output Valid tCO 70 ns or CE to Output Active tCOE 5 ns 5
Output High-Z from Deselection tOD 25 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR1
tWR2
15 ns
ns
12
13
Output High-Z from WE tODW 25 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 30 ns 4
Data Hold Time tDH1
tDH2
0
10 ns
ns
12
13
DS1249Y/AB
READ CYCLE SEE NOTE 1
WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1249Y/AB
WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION SEE NOTE 11
