DS1250Y-70 ,4096K Nonvolatile SRAMDS1250Y/AB4096k Nonvolatile SRAMwww.dalsemi.com
DS1250Y-70 ,4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
DS1250Y-70+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250Y-70IND+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250YP-100 ,4096K Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250YP-100IND ,4096k Nonvolatile SRAMDS1250Y/AB4096k Nonvolatile SRAMwww.dalsemi.com
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC113ZUA , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC114 , NPN Small Signal Transistor Small Signal Diode
DTC114E ,NPN SILICON BIAS RESISTOR TRANSISTORELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DS1250AB-100-DS1250ABP-100IND-DS1250ABP-100IND+-DS1250ABP-70IND-DS1250Y-100-DS1250Y-70-DS1250YP-100IND-DS1250YP-100IND+-DS1250YP-70IND
4096k Nonvolatile SRAM
FEATURES10 years minimum data retention in the
absence of external powerData is automatically protected during powerlossReplaces 512k x 8 volatile static RAM,
EEPROM or Flash memoryUnlimited write cyclesLow-power CMOSRead and write access times as fast as 70 nsLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first timeFull ±10% VCC operating range (DS1250Y)Optional ±5% VCC operating range
(DS1250AB)Optional industrial temperature range of
-40°C to +85°C, designated INDJEDEC standard 32-pin DIP packageNew PowerCap Module (PCM) packageDirectly surface-mountable moduleReplaceable snap-on PowerCap provideslithium backup batteryStandardized pinout for all nonvolatile
SRAM productsDetachment feature on PCM allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTIONA0 - A18- Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+5V)GND - Ground
DS1250Y/AB
4096k Nonvolatile SRAM32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
DQ1
DQ0
VCC
DQ7
DQ5
DQ6
A16
A12
A18
DQ2
GND
DQ4
DQ3NCA15A16NCVCC
WEOECEDQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GND
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
DS1250Y/AB
DESCRIPTIONThe DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as
524,288 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250 devices can be used in place of existing 512k x8 static RAMs directly conforming to the popular byte-wide 32-pin DIP standard. DS1250 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODEThe DS1250 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs (A0 -
A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the eightdata output drivers within tACC (Access Time) after the last address input signal is stable, providing that and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied,
then data access must be measured from the later-occurring signal (CE or OE) and the limiting parameter
is either tCO for CE or tOE for OE rather than address access.
WRITE MODEThe DS1250 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODEThe DS1250AB provides full functional capability for VCC greater than 4.75 volts and write protects by4.5 volts. The DS1250Y provides full functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithiumenergy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1250AB and 4.5 volts for the
DS1250Y.
FRESHNESS SEALEach DS1250 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,guaranteeing full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium
energy source is enabled for battery back-up operation.
DS1250Y/AB
PACKAGESThe DS1250 is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-pin
DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250 PCMdevice to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250 PCM module base is reflow soldered, a DS9034PC
PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC
is keyed to prevent improper attachment. DS1250 module bases and DS9034PC PowerCaps are ordered
separately and shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +7.0VOperating Temperature 0°C to 70°C, -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C, -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditionsabove those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
DC ELECTRICAL (VCC=5V ±=5% for DS1250AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1250Y)
DS1250Y/AB
CAPACITANCE (tA=25°C)
AC ELECTRICAL (VCC=5V ±=5% for DS1250AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1250Y)
DS1250Y/AB
READ CYCLESEE NOTE 1
WRITE CYCLE 1SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1250Y/AB
WRITE CYCLE 2SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITIONSEE NOTE 11