DS1250W-150+ ,3.3V 4096k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the A18 1 32 V CCabsence of extern ..
DS1250WP-150 ,3.3V 4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
DS1250WP-150 ,3.3V 4096K Nonvolatile SRAMPIN DESCRIPTIONA0 - A18 - Address InputsDQ0 - DQ7 - Data In/Data OutCE - Chip EnableWE - Write Enab ..
DS1250Y ,4096k Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the A18 1 32 V CCabsence of extern ..
DS1250Y/70IND+ ,4096k Nonvolatile SRAM 19-5647; Rev 12/10 DS1250Y/AB 4096k Nonvolatile SRAM
DS1250Y-100 ,4096K Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in theA18 32 V1 CCabsence of external powe ..
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DS1250W-150-DS1250W-150+
3.3V 4096k Nonvolatile SRAM
FEATURES 10 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Replaces 512k x 8 volatile static RAM,
EEPROM or Flash memory Unlimited write cycles Low-power CMOS Read and write access times of 100ns Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time Optional industrial temperature range of -
40°C to +85°C, designated IND JEDEC standard 32-pin DIP package PowerCap Module (PCM) package
– Directly surface-mountable module
– Replaceable snap-on PowerCap provides
lithium backup battery
– Standardized pinout for all nonvolatile
SRAM products
– Detachment feature on PCM allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION A0 - A18 - Address Inputs
DQ0 - DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+3.3V)
GND - Ground
DS1250W
3.3V 4096k Nonvolatile SRAM 19-5648; Rev 12/10
13
10
11
12
14
31
32-Pin Encapsulated Package
740-Mil Extended A14A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20 A16
A12
A6
A18
DQ2
GND
15
16
18
17
DQ4
DQ3
WE
NC A15
A16 NC VCC
OE
CE DQ7 DQ6
DQ5 DQ4
DQ3
DQ2 DQ1
DQ0
GND 5 6 8 9
10 11
12 13
14 15
16
17
A17 A14 33 32
31 30
29 28 27
26 25
24
23 22
21
20 19
18
A13
A12 A11
A10 A9 A8
A7 A6
A5 A4
A3 A2
A1
A0
34 A18
GND VBAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
DS1250W
DESCRIPTION The DS1250W 3.3V 4096k Nonvolatile SRAM is a 4,194,304-bit, fully static, nonvolatile SRAM
organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250W devices can be used in place of existing 512k
x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1250W devices in
the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE The DS1250W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 - A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE The DS1250W executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE The DS1250W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
FRESHNESS SEAL Each DS1250W device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 3.0 volts, the lithium energy source
is enabled for battery back-up operation.
PACKAGES The DS1250W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
DS1250W
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250W PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250W module base is reflow soldered, a DS9034PC PowerCap
is snapped on top of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to
prevent improper attachment. DS1250W module bases and DS9034PC PowerCaps are ordered separately
and shipped in separate containers. See the DS9034PC data sheet for further information.
DS1250W
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperature
EDIP -40°C to +85°C
PowerCap -55°C to +125°C
Lead Temperature (soldering, 10s) +260°C
Soldering Temperature (reflow, PowerCap) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage VCC 3.0 3.3 3.6 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 +0.4 V
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -1.0 +1.0 µA
I/O Leakage Current CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.2V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE=2.2V ICCS1 50 250 µA
Standby Current CE=VCC-0.2V ICCS2 30 150 µA
Operating Current ICCO1 50 mA
Write Protection Voltage VTP 2.8 2.9 3.0 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 5 10 pF
Input/Output Capacitance CI/O 5 10 pF
DS1250W
AC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL DS1250W-100 UNITS NOTES MIN MAX Read Cycle Time tRC 100 ns
Access Time tACC 100 ns to Output Valid tOE 50 ns to Output Valid tCO 100 ns or CE to Output Active tCOE 5 ns 5
Output High-Z from Deselection tOD 35 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 100 ns
Write Pulse Width tWP 75 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR1
tWR2
20 ns 12
13
Output High-Z from WE tODW 35 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 40 ns 4
Data Hold Time tDH1
tDH2
20 ns 12
13
READ CYCLE SEE NOTE 1
DS1250W
WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
