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DS1265W-100IND-DS1265W-100IND+
3.3V 8Mb Nonvolatile SRAM
FEATURES 10 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Unlimited write cycles Low-power CMOS operation Read and write access times of 100ns Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time Optional industrial (IND) temperature range
of -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTION A0–A19 - Address Inputs
DQ0–DQ7 - Data In/Data Out - Chip Enable - Write Enable - Output Enable
VCC - Power (+3.3V)
GND - Ground
NC - No Connect
DESCRIPTION The DS1265W 8Mb nonvolatile (NV) SRAMs are 8,388,608-bit, fully static, NV SRAMs organized as
1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles that can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1265W
3.3V 8Mb Nonvolatile SRAM 19-5617; Rev 11/10
13
10
11
12
14
35
36-Pin Encapsulated Package
740mil Extended A18A14
A7
A6
A5
A4
A3
A2
A0
A1
VCC
A19
NC
A15
A17
WE
A13
A8
A9
A11
OE
A10
DQ7
CE
36
34
33
32
31
30
29
28
27
26
25
23
24 NC
A16
A12
NC
DQ0
DQ1
15
16
22
21
DQ6
DQ5
17
18 GND
DQ2
DQ3
DQ4
19
20
DS1265W
READ MODE The DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 20 address inputs
(A0–A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either
tCO for CE or tOE for OE rather than tACC.
WRITE MODE The DS1265 devices execute a write cycle whenever WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active), then WE
will disable the outputs in tODW from its falling edge.
DATA-RETENTION MODE The DS1265W provides full functional capability for VCC greater than 3.0V and write protects by 2.8V.
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 2.5V, the power-switching circuit
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 3.0V.
FRESHNESS SEAL Each DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
DS1265W
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperature Range -40°C to +85°C
Lead Temperature (soldering, 10s) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power-Supply Voltage VCC 3.0 3.3 3.6 V
Logic 1 Input Voltage VIH 2.2 VCC V
Logic 0 Input Voltage VIL 0.0 +0.4 V
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 3.3V ±0.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL -2.0 +2.0 µA
I/O Leakage Current IIO -2.0 +2.0 µA
Output Current at 2.2V IOH -1.0 mA
Output Current at 0.4V IOL 2.0 mA
Standby Current CE= 2.2V ICCS1 150 250 µA
Standby Current CE= VCC - 0.2V ICCS2 100 150 µA
Operating Current ICCO1 50 mA
Write Protection Voltage VTP 2.8 2.9 3.0 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 10 20 pF
Input/Output Capacitance CI/O 10 20 pF
DS1265W
AC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 3.3V ±0.3V)
PARAMETER SYMBOL
DS1265W-100 UNITS NOTES MIN MAX Read Cycle Time tRC 100 ns
Access Time tACC 100 ns to Output Valid tOE 50 ns to Output Valid tCO 100 ns or CE to Output Active tCOE 5 ns 5
Output High-Z from Deselection tOD 35 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 100 ns
Write Pulse Width tWP 75 ns 3
Address Setup Time tAW 0 ns
Write Recovery Time tWR1
tWR2
20 ns
ns
12
13
Output High-Z from WE tODW 35 ns 5
Output Active from WE tOEW 5 ns 5
Data Setup Time tDS 40 ns 4
Data Hold Time tDH1
tDH2
20 ns
ns
12
13
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
DS1265W
TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1265W
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Fail Detect to CE and WE Inactive tPD 1.5 µs 11
VCC Slew from VTP to 0V tF 150 µs
VCC Slew from 0V to VTP tR 150 µs
VCC Valid to CE and WE Inactive tPU 2 ms
VCC Valid to End of Write Protection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data-Retention Time tDR 10 years 9
WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES: 1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE or WE. tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
