DS1267S-050/TR ,Dual Digital Potentiometer ChipDS1267Dual Digital Potentiometer Chipwww.dalsemi.com
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DS1267S-100+ ,±5V Dual Digital Potentiometer ChipDS1267Dual Digital Potentiometer Chipwww.dalsemi.com
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DS1267-010-DS1267-050-DS1267-100-DS1267E-010/TR-DS1267S-010-DS1267S-010/TR-DS1267S-050-DS1267S-050/TR-DS1267S-100
Dual Digital Potentiometer Chip
RST
CLK
GND
SOUT
COUT
16-Pin SOIC (300-mil)
See Mech. Drawings Section
FEATURES Ultra-low power consumption, quiet,
pumpless design Two digitally controlled, 256-positionpotentiometers Serial port provides means for setting and
reading both potentiometers Resistors can be connected in series to
provide increased total resistance 14-pin DIP, 16-pin SOIC, 20-pin TSSOPpackages Resistive elements are temperature
compensated to ±0.3 LSB relative linearity Standard resistance values:DS1267-10 ~ 10 kWDS1267-50 ~ 50 kWDS1267-100 ~ 100 kW Operating Temperature Range: Industrial: -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTIONSL0, L1-Low End of Resistor
H0, H1-High End of Resistor
W0, W1-Wiper Terminal of Resistor-Substrate Bias Voltage
SOUT-Stacked Configuration Output
RST-Serial Port Reset Input-Serial Port Data Input
CLK-Serial Port Clock Input
COUT-Cascade Port Output
VCC-+5 Volt Supply
GND-Ground-No Internal Connection
14-Pin DIP (300-mil)See Mech. Drawings Section
SOUT
Dual Digital Potentiometer ChipVCC
SOUT
DS1267
DESCRIPTIONThe DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-statepotentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device are accomplished via a 3-wire serial port interface.
This interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the
same resolution. For multiple-device, single-processor environments, the DS1267 can be cascaded or
daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1267 is offered in three standard resistance values which include 10, 50, and 100-kohm versions.
Available packages for the device include a 14-pin DIP, 16-pin SOIC, and 20-pin TSSOP.
OPERATIONThe DS1267 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions
and the stack select bit when the device is powered. A block diagram of the DS1267 is presented in
Figure 1.
Communication and control of the DS1267 are accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST,
CLK, and DQ.
The RST control signal is used to enable the 3-wire serial port operation of the device. The chip is
selected when RST is high; RST must be high to begin any communication to the DS1267. The CLK
signal input is used to provide timing synchronization for data input and output. The DQ signal line is
used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shiftregister of the DS1267.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST
signal input is low. Communication with the DS1267 requires the transition of the RST input from a low
state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to
high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing
diagrams of Figure 9(b)-(c).
Data written to the DS1267 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit, which will be discussed in the section entitled "StackedConfiguration." Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting.
Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the
MSB for the wiper position occupying bit 9 and the LSB bit 16.
DS1267
DS1267 BLOCK DIAGRAM Figure 1
I/O SHIFT REGISTER Figure 2Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1267, 17 bits (or some integer multiple) of data shouldalways be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the
register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed, the RST signal input should be taken to a low
state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state,
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a RST transition to the inactive state. On device power-up
the DS1267 wiper positions will be set at 50% of the total resistance or binary value 1000 0000.
DS1267
STACKED CONFIGURATIONThe potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to asthe stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/Oshift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, SOUT, will be that of the
potentiometer-1 wiper.
STACKED CONFIGURATION Figure 3
CASCADE OPERATIONA feature of the DS1267 is the ability to control multiple devices from a single processor. Multiple
DS1267s can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267 a bit will appear at the COUT output within a maximum delay of 50 nanoseconds.
The stack select bit of the DS1267 will always be the first out the part at the beginning of a transaction.
Additionally the COUT pin is always active regardless of the state of RST. This allows one to read the I/O
shift register without changing its value.
CASCADING MULTIPLE DEVICES Figure 4
DS1267
The COUT output of the DS1267 can be used to drive the DQ input of another DS1267. When connectingmultiple devices, the total number of bits transmitted is always 17 times the number of DS1267s in the
daisy chain.
An optional feedback resistor can be placed between the COUT terminal of the last device and the first
DS1267 DQ input, thus allowing the controlling processor to read as well as write data or circularly clock
data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1to 10 kohms.
When reading data via the COUT pin and isolation resistor, the DQ line is left floating by the reading
device. When RST is driven high, bit 17 is present on the COUT pin, which is fed back to the input DQ
pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the
first position of the I/O shift register and bit 16 becomes present on COUT and DQ of the next device. After17 bits (or 17 times the number of DS1267s in the daisy chain), the data has shifted completely around
and back to its original position. When RST transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
ABSOLUTE AND RELATIVE LINEARITYAbsolute linearity is defined as the difference between the actual measured output voltage and the
expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolutelinearity is given in terms of a minimum increment or expected output when the wiper is moved one
position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 10/512 volts.
The equation for absolute linearity is given as follows:
(1)ABSOLUTE LINEARITY
AL={VO (actual) - VO (expected)}/MI
Relative Linearity is a measure of error between two adjacent wiper position points and is given in terms
of MI by equation (2).
(2)RELATIVE LINEARITYRL={VO (n+1) - VO (n)}/MI
Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267 at 25°C.
The specification for absolute linearity of the DS1267 is ±0.75 MI typical. The specification for relativelinearity of the DS1267 is ±0.3 MI typical.
DS1267
LINEARITY MEASUREMENT CONFIGURATION Figure 5
NOTE:In this setup, a ±2% delta in total resistance R0 to R1 would cause a ±2.5 MI error.
DS1267 ABSOLUTE AND RELATIVE LINEARITY Figure 6
TYPICAL APPLICATION CONFIGURATIONSFigures 7 and 8 show two typical application configurations for theDS1267. By connecting the wiper
terminal of the part to a high-impedance load, the effects of the wiper resistance is minimized, since the
wiper resistance can vary from 400 to 1000ohms depending on wiper voltage. Figure 7 presents thedevice connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by
the following equation:
Av = -n/(255-n); where n = 0 to 255
Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to
