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DS1270AB-100IND |DS1270AB100INDDALLASN/a3avai16M Nonvolatile SRAM
DS1270AB-70 |DS1270AB70DALLASN/a2000avai16M Nonvolatile SRAM
DS1270AB-70IND |DS1270AB70INDDALLASN/a1avai16M Nonvolatile SRAM
DS1270Y-100IND |DS1270Y100INDDALLASN/a30avai16M Nonvolatile SRAM
DS1270Y-70 |DS1270Y70DSN/a5avai16M Nonvolatile SRAM
DS1270Y-70IND |DS1270Y70INDDALLASN/a250avai16M Nonvolatile SRAM


DS1270AB-70 ,16M Nonvolatile SRAM DS1270Y/AB 16M Nonvolatile SRAM
DS1270AB-70# ,16M Nonvolatile SRAM19-5615; Rev 11/10 DS1270Y/AB 16M Nonvolatile SRAM
DS1270AB-70IND ,16M Nonvolatile SRAMFEATURES PIN ASSIGNMENT 5 years minimum data retention in the NC 1 36 V CCabsence of external ..
DS1270W-100IND ,3.3V 16Mb Nonvolatile SRAMPIN DESCRIPTION A0–A20 - Address Inputs DQ0–DQ7 - Data In/Data Out CE - Chip Enable WE - Wri ..
DS1270W-150# ,3.3V 16Mb Nonvolatile SRAMFEATURES PIN ASSIGNMENT  Five years minimum data retention in the NC 1 36 V CCabsence of exter ..
DS1270Y ,16M NV SRAMFEATURES PIN ASSIGNMENT  5 years minimum data retention in the NC 1 36 V CCabsence of external ..
DTC114TCA ,Conductor Holdings Limited - Digital Transistor
DTC114TE ,Pre-biased TransistorsMaximum ratings are those values beyond which device damage can occur.M = Date Code
DTC114TE TL , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC114TET1 ,Bias Resistor TransistorTransistor) contains a single transistor with a monolithic bias networkconsisting of two resistors; ..
DTC114TET1G ,Bias Resistor TransistorTransistor) contains a single transistor with a monolithic bias networkconsisting of two resistors; ..
DTC114TK , DTA/DTC SERIES


DS1270AB-100IND-DS1270AB-70-DS1270AB-70IND-DS1270Y-100IND-DS1270Y-70-DS1270Y-70IND
16M Nonvolatile SRAM
FEATURES
��5 years minimum data retention in the
absence of external power
��Data is automatically protected during power
loss
��Unlimited write cycles
��Low-power CMOS operation
��Read and write access times as fast as 70 ns
��Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
��Full ±10% VCC operating range (DS1270Y)
��Optional ±5% VCC operating range
(DS1270AB)
��Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
PIN DESCRIPTION
A0 – A20 - Address Inputs
DQ0 - DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable VCC - Power (+5V)
GND - Ground
NC - No Connect
DESCRIPTION

The DS1270 16M Nonvolatile SRAMs are 16,777,216-bit, fully static nonvolatile SRAMs organized as
2,097,152 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1270Y/AB
16M Nonvolatile SRAM

36-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A18
A14
VCC
NC
WE
OE
DQ7
CE
A20
A16
A12
DQ0
DQ1
DQ6
DQ5 GND
DQ2
DQ3
DQ4
DS1270Y/AB
READ MODE

The DS1270 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 21 address inputs (A0 - A20) defines which of the 2,097,152 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting
parameter is either tCO for CE or tOE for OE rather than tACC.
WRITE MODE

The DS1270 devices execute a write cycle whenever WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE
will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE

The DS1270AB provides full-functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1270Y provides full-functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become don’t care, and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1270AB and 4.5 volts for the
DS1270Y.
FRESHNESS SEAL
Each DS1270 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy source is enabled for battery backup operation.
DS1270Y/AB
ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature 0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)

DC ELECTRICAL (VCC=5V ±=5% for DS1270AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1270Y)
CAPACITANCE (tA=25°C)

DS1270Y/AB
AC ELECTRICAL (VCC=5V ±=5% for DS1270AB)
CHARACTERISTICS (tA: See Note 10) (VCC=5V ±=10% for DS1270Y)
TIMING DIAGRAM: READ CYCLE SEE NOTE 1
DS1270Y/AB
TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1270Y/AB
POWER-DOWN/POWER-UP CONDITION SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (tA: See Note 10)
(tA=25°C)
WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:

1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period.
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