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DS12C887-DS12C887.
Real time clock
FEATURESDrop-in replacement for IBM AT computer
clock/calendarPin compatible with the MC146818B and
DS1287Totally nonvolatile with over 10 years of
operation in the absence of powerSelf-contained subsystem includes lithium,quartz, and support circuitry.Counts seconds, minutes, hours, days, day of
the week, date, month, and year with leap
year compensation valid up to 2100Binary or BCD representation of time,calendar, and alarm12– or 24–hour clock with AM and PM in
12–hour modeDaylight Savings Time optionSelectable between Motorola and Intel bustimingMultiplex bus for pin efficiencyInterfaced with software as 128 RAM
locations– 15 bytes of clock and control registers
– 113 bytes of general purpose RAMProgrammable square wave output signalBus–compatible interrupt signals (IRQ)Three interrupts are separately softwaremaskable and testable
– Time–of–day alarm once/second to
once/day
– Periodic rates from 122 ms to 500 ms
– End of clock update cycleCentury register
PIN ASSIGNMENT
PIN DESCRIPTIONAD0-AD7-Multiplexed Address/Data Bus-No Connect
MOT-Bus Type Selection-RTC Chip Select Input-Address Strobe
R/W-Read/Write Input-Data Strobe
RESET-Reset Input
IRQ-Interrupt Request Output
SQW-Square Wave Output
VCC-+5 Volt Main Supply
GND-Ground
DESCRIPTIONThe DS12C887 Real Time Clock plus RAM is designed as a direct upgrade replacement for the DS12887in existing IBM compatible personal computers to add hardware year 2000 compliance. A century bytewas added to memory location 50, 32h, as called out by the PC AT specification. A lithium energysource, quartz crystal, and write-protection circuitry are contained within a 24–pin dual in-line package.As such, the DS12C887 is a complete subsystem replacing 16 components in a typical application. Thefunctions include a nonvolatile time-of-day clock, an alarm, a one-hundred-year calendar, programmable
DS12C887
Real Time ClockMOT
DS12C887 24-Pin
ENCAPSULATED PACKAGE
AD1
AD3
AD4
AD5
AD6
AD7
GND
VCC
SQW
IRQ
RESET
R/W
AD0
AD2
DS12C887
OPERATIONThe block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS12C887. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts areapplied within normal limits, the device is fully accessible and data can be written and read. When VCC is
below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continuesunaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are
switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of ±1
minute per month at 25°C regardless of the voltage input on the VCC pin.
MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. Whenconnected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pull-down resistance of approximately 20KΩ.
SQW (Square Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE
bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts typical.
AD0-AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins becauseaddress information and data information time share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS12C887 since the
bus change from address to data occurs during the internal RAM access time. Addresses must be valid
prior to the falling edge of AS/ALE, at which time the DS12C887 latches the address from AD0 to AD6.Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a
read cycle the DS12C887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read
cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of
Motorola timing or as RD transitions high in the case of Intel timing.
AS (Address Strobe Input) – A positive going address strobe pulse serves to demultiplex the bus. Thefalling edge of AS/ALE causes the address to be latched within the DS12C887. The next rising edge that
occurs on the AS bus will clear the address regardless of whether CS is asserted. Access commands
should be sent in pairs.
DS (Data Strobe or Read Input) – The DS/RD pin has two modes of operation depending on the levelof the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode
DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read
cycles, DS signifies the time that the DS12C887 is to drive the bidirectional bus. In write cycles the
trailing edge of DS causes the DS12C887 to latch the written data. When the MOT pin is connected to
GND, Intel bus timing is selected. In this mode the DS pin is called Read(RD). RD identifies the timeperiod when the DS12C887 drives the bus with read data. The RD signal is the same definition as the
Output Enable (OE) signal on a typical memory.
DS12C887
W
(Read/Write Input) – The R/W pin also has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/W while DS is high. A write cycle is
indicated when R/W is low during DS. When the MOT pin is connected to GND for Intel timing, theW signal is an active low signal called WR. In this mode the R/W pin has the same meaning as the
Write Enable signal (WE) on generic RAMs.
(Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12C887to be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD
and WR for Intel timing. Bus cycles which take place without asserting CS will latch addresses but noaccess will occur. When VCC is below 4.25 volts, the DS12C887 internally inhibits access cycles by
internally disabling the CS input. This action protects both the real time clock data and RAM data duringpower outages.
IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS12C887 that can be
used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin the processor
program normally reads the C register. The RESET pin also clears pending interrupts. When no interrupt
conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be
connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pull-up resistor.
RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power-up the
RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of
time that RESET is held low is dependent on the application. However, if RESET is used on power–up,
the time RESET is low should exceed 200 ms to make sure that the internal timer that controls the
DS12C887 on power-up has timed out. When RESET is low and VCC is above 4.25 volts, the followingoccurs:
A. Periodic Interrupt Enable (PEI) bit is cleared to zero.
B. Alarm Interrupt Enable (AIE) bit is cleared to zero.
C. Update Ended Interrupt Flag (UF) bit is cleared to zero.
D. Interrupt Request Status Flag (IRQF) bit is cleared to zero.E. Periodic Interrupt Flag (PF) bit is cleared to zero.
F. The device is not accessible until RESET is returned high.G. Alarm Interrupt Flag (AF) bit is cleared to zero.
H. IRQ pin is in the high impedance state.
I. Square Wave Output Enable (SQWE) bit is cleared to zero.
J. Update Ended Interrupt Enable (UIE) is cleared to zero.
In a typical application RESET can be connected to VCC . This connection will allow the DS12C887 togo in and out of power fail without affecting any of the control registers.
DS12C887
DS12C887 BLOCK DIAGRAM Figure 1
DS12C887
POWER-DOWN/POWER-UP CONSIDERATIONSThe Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the
DS12C887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms,
provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A).
This time period allows the system to stabilize after power is applied. When VCC falls below 4.25 volts,
the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin.The DS12C887 is, therefore, write-protected. When the DS12C887 is in a write-protected state, all inputs
are ignored and all outputs are in a high impedance state. When VCC falls below a level of approximately
3 volts, the external VCC supply is switched off and an internal lithium energy source supplies power to
the Real Time Clock and the RAM memory.
RTC ADDRESS MAPThe address map for the DS12C885 is shown in Figure 2. The address map consists of 113 bytes of user
RAM, 11 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used
for control and status. All 128 bytes can be directly written or read except for the following:
1. Registers C and D are read-only.2. Bit-7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
DS12C887 REAL TIME CLOCK ADDRESS MAP Figure 2
DS12C887
TIME, CALENDAR AND ALARM LOCATIONSThe time and calendar information is obtained by reading the appropriate memory bytes. The time,
calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten
time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before
writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a
logic one to prevent updates from occurring while access is being attempted. In addition to writing the tentime, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of
Register B must be set to the appropriate logic level. All ten time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be cleared after the data mode bit has been written to
allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock
makes all updates in the selected mode. The data mode cannot be changed without reinitializing the tendata bytes. Table 2 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The
24–12 bit cannot be changed without reinitializing the hour locations. When the 12–hour format is
selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar,
and alarm bytes are always accessible because they are double buffered. Once per second the eleven bytes
are advanced by one second and checked for an alarm condition. If a read of the time and calendar dataoccurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The
probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible
incorrect time and calendar reads are covered later in this text. The three alarm bytes can be used in two
ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm
locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high . Thesecond use condition is to insert a “don’t care” state in one or more of the three alarm bytes. The “don’t
care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the
“don’t care” condition when at logic 1. An alarm will be generated each hour when the “don’t care” bits
are set in the hours byte. Similarly, an alarm is generated every minute with “don’t care” codes in the
hours and minute alarm bytes. The “don’t care” codes in all three alarm bytes create an interrupt everysecond.
TIME, CALENDAR AND ALARM DATA MODES Table 1
DS12C887
CONTROL REGISTERSThe DS12C887 has four control registers which are accessible at all times, even during the update cycle.
REGISTER A
MSB LSB
UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, theupdate transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244μs.
The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The
UIP bit is read-only and is not affected by RESET. Writing the SET bit in Register B to a 1 inhibits any
update transfer and clears the UIP status bit.
DV2, DV1, DV0 - These three bits are used to turn the oscillator on or off and to reset the countdownchain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC
to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next
update will occur at 500 ms after a pattern of 010 is written to DV0, DV1, and DV2.
RS3, RS2, RS1, RS0 - These four rate-selection bits select one of the 13 taps on the 15-stage divider ordisable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
1. Enable the interrupt with the PIE bit;
2. Enable the SQW output pin with the SQWE bit;3. Enable both at the same time and the same rate; or
4. Enable neither
Table 1 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RS
bits. These four read/write bits are not affected by RESET
.
DS12C887
REGISTER B
MSB LSB
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per
second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. SET is a read/write bit and is not affected by RESET or internal functionsof the DS12C887.
PIE - The Periodic Interrupt Enable bit is a read/write bit which allows the Periodic Interrupt Flag (PF)
bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated
by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the PIE bit
blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set
at the periodic rate. PIE is not modified by any internal DS12C887 functions but is cleared to 0 on
RESET.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm
Flag (AF) bit in register C to assert IRQ. An alarm interrupt occurs for each second that the 3 time bytes
equal the 3 alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is
set to 0, the AF bit does not initiate the IRQ signal. The internal functions of the DS12C887 not affect
the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write bit that enables the Update End Flag
(UF) bit in Register C to assert IRQ. The RESET pin going low or the SET bit going high clears the
UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequency
set by the rate-selection bits RS3 through RS0 is driven out on the SQW pin. When the SQWE bit is set
to 0, the SQW pin is held low. SQWE is a read/write bit and is cleared by RESET. SQWE is set to a 1
when VCC is powered up.
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit
is not modified by internal functions or RESET. A 1 in DM signifies binary data while a 0 in DM
specifies Binary Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and
a 0 indicates the 12-hour mode. This bit is read/write and is not affected by internal functions or RESET.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when
DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On
the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
DS12C887
REGISTER C
MSB LSB
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
i.e., IRQF = (PF ● PIE) + (AF ● AIE) + (UF ● UIE)
Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after
Register C is read by the program or when the RESET pin is low.
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1’s, the IRQ signal is active and will
set the IRQF bit. The PF bit is cleared by a software read of Register C or a RESET.
AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time.
If the AIE bit is also a 1, the IRQ pin will go low and a 1 will appear in the IRQF bit. A RESET or a read
of Register C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to
1, the 1 in UF causes the IRQF bit to be a 1, which will assert the IRQ pin. UF is cleared by reading
Register C or a RESET.
BIT 3 THROUGH BIT 0 - These are unused bits of the status Register C. These bits always read 0 and
cannot be written.
REGISTER D
MSB LSB
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the battery connected to the VBAT
pin. This bit is not writeable and should always be a 1 when read. If a 0 is ever present, an exhausted
internal lithium energy source is indicated and both the contents of the RTC data and RAM data are
questionable. This bit is unaffected by RESET.
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,
when read, they will always read 0.
DS12C887
CENTURY REGISTER
The century register at location 32h, is a BCD register designed to automatically load the BCD value 20
as the year register changes from 99 to 00. The MSB of this register will not be affected when the load of
20 occurs and will remain at the value written by the user.
NONVOLATILE RAM
The 113 general purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS12C887. They can be used by the processor program as nonvolatile memory and are fully availableduring the update cycle.
INTERRUPTS
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500ms to 122μs. The update-ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register Benable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated
when the event occurs. A zero in an interrupt-enable bit prohibits the IRQ pin from being asserted from
that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is
immediately set at an active level, although the interrupt initiating the event may have occurred much
earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before
first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set
independent of the state of the corresponding enable bit in Register B. The flag bit can be used in a
polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which
software can interrogate as necessary. When a flag is set, an indication is given to software that an
interrupt event has occurred since the flag bit was last read; however, care should be taken when using theflag bits as they are cleared each time Register C is read. Double latching is included with Register C so
that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared
when read and new interrupts which are pending during the read cycle are held until after the cycle is
completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be
examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as at
least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is
a one whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is
accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts
have been initiated by the DS12C887. The act of reading Register C clears all active flag bits and theIRQF bit.
