DS12CR887-5+ ,RTCs with Constant-Voltage Trickle ChargerELECTRICAL CHARACTERISTICS(V = V to V , T = -40°C to +85°C, (DS12R887-33 and DS12R887-5, T = -20°C ..
DS12R885-33 ,RTC with Constant-Voltage Trickle ChargerELECTRICAL CHARACTERISTICS(V = V to V , T = -40°C to +85°C, unless otherwise noted.) (Note 1)CC CC( ..
DS12R885-5 ,RTC with Constant-Voltage Trickle ChargerELECTRICAL CHARACTERISTICS (DS12R885 Only)(V = 0V, V = 3.2V, T = -40°C to +85°C, unless otherwise n ..
DS12R887-33 ,RTC with Constant-Voltage Trickle ChargerFeaturesThe DS12R885 is a functional drop-in replacement for♦ Trickle-Charge Capability for a Recha ..
DS12R887-5 ,RTC with Constant-Voltage Trickle ChargerApplications♦ +5.0V or +3.3V Operation♦ Industrial Temperature RangeEmbedded Systems♦ DS12CR887 Enc ..
DS1302 ,Trickle Charge Timekeeping ChipPIN DESCRIPTIONDS1302S-16 16-Pin SOIC (300-mil) X1, X2 - 32.768kHz Crystal PinsDS1302SN-16 16-Pin S ..
DTC114YET1 ,Bias Resistor Transistor3DTC114YEMINIMUM RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONSSurface mount board layout ..
DTC114YET1G ,Bias Resistor TransistorTHERMAL CHARACTERISTICSSee detailed ordering, marking, and shipping information inthe package dimen ..
DTC114YETL , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC114YKA T146 , NPN 100mA 50V Digital Transistors
DTC114YKAT146 , NPN 100mA 50V Digital Transistors
DTC114YKA-T146 , NPN 100mA 50V Digital Transistors
DS12CR887/5+-DS12CR887-33+-DS12CR887-5+
RTCs with Constant-Voltage Trickle Charger
General DescriptionThe DS12R885 is a functional drop-in replacement for
the DS12885 real-time clock (RTC). The device pro-
vides an RTC/calendar, one time-of-day alarm, three
maskable interrupts with a common interrupt output, a
programmable square wave, and 114 bytes of battery-
backed static RAM. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including correction for leap years. It also oper-
ates in either 24-hour or 12-hour format with an AM/PM
indicator. A precision temperature-compensated circuit
monitors the status of VCC. If a primary power failure is
detected, the device automatically switches to a back-
up supply. The VBACKUPpin supports a rechargeable
battery or a super cap and includes an integrated,
always enabled trickle charger. The DS12R885 is
accessed through a multiplexed byte-wide interface,
which supports both Intel and Motorola modes. The
DS12CR887 and DS12R887 integrate the DS12R885
die with a crystal and battery.
ApplicationsEmbedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
FeaturesTrickle-Charge Capability for a Rechargeable
Battery or Super CapSelectable Intel or Motorola Bus TimingRTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year with Leap-Year Compensation to
2100Interrupt Output with Three Independently
Maskable Interrupt FlagsTime-of-Day Alarm is Once-per-Second to Once-
per-DayPeriodic Rates from 122μs to 500msEnd-of-Clock Update Cycle Flag14 Bytes of Clock and Control Registers114 Bytes of General-Purpose Battery-Backed NV
RAM with Clear InputProgrammable Square-Wave OutputAutomatic Power-Fail Detect and Switch Circuitry+5.0V or +3.3V OperationIndustrial Temperature RangeDS12CR887 Encapsulated DIP (EDIP) Module with
Integrated Battery and CrystalDS12R887 BGA Module Surface-Mountable
Package with Integrated Crystal and
Rechargeable Battery
DS12R885/DS12CR887/
DS12R887
RTCs with Constant-Voltage Trickle ChargerDS12R885DS83C520
R/W
GNDX1
VCC
VCC
CRYSTAL
VBACKUP
SUPER
CAP
AD(0–7)SQW
RESET
IRQ
RCLR
MOT
Typical Operating Circuit
PART TEMP RANGE PIN-
PACKAGE TOP MARK*
DS12R885S-5+ -40°C to +85°C 24 SO
(300 mils) DS12R885-5
DS12R885S-5+
T&R -40°C to +85°C 24 SO
(300 mils) DS12R885-5
DS12R885S-33+ -40°C to +85°C 24 SO
(300 mils) DS12R885-33
DS12R885S-33+
T&R -40°C to +85°C 24 SO
(300 mils) DS12R885-33
DS12CR887-5+ -40°C to +85°C 24 EDIP
(700 mils) DS12CR887-5
DS12CR887-33+ -40°C to +85°C 24 EDIP
(700 mils) DS12CR887-33
DS12R887-5 -20°C to +60°C 48 BGA DS12R887-5
DS12R887-33 -20°C to +60°C 48 BGA DS12R887-33
Pin Configurations appear at end of data sheet.+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*A “+” anywhere on the top mark indicates a lead(Pb)-free
Ordering Information
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCCPin Relative to Ground.....-0.3V to +6.0V
Operating Temperature Range...........................-40°C to +85°C
Operating Temperature Range
(DS12R887-33 and DS12R887-5)....................-20°C to +60°C
Operating Temperature Range (All others).........-20°C to +60°C
Storage Temperature Range
EDIP..................................................................-40°C to +85°C
SO...................................................................-55°C to +125°C
BGA..................................................................-20°C to +60°C
Lead Temperature (soldering, 10s).................................+260°C
(Note:EDIP is hand or wave-soldered only.)
Soldering Temperature (reflow)
SO.................................................................................+260°C
BGA...............................................................................+225°C
DC ELECTRICAL CHARACTERISTICS(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, (DS12R887-33 and DS12R887-5, TA = -20°C to +60°C), unless otherwise noted.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS-33 2.97 3.3 3.63 Supply Voltage (Note 2) VCC-5 4.5 5.0 5.5 V
VBACKUP Input Voltage
(DS12R885 Only) VBACKUP (Note 2) 2.0 VOUT V
Input Logic 1 VIH (Note 2) 2.2 VCC +
0.3 V
Input Logic 0 VIL (Note 2) -0.3 +0.8 V
-330.72VCC Power-Supply Current
(Note 3) ICC1-5 0.8 2 mA 0.2500.5VCC Standby Current (Note 4) ICCS-330.1400.3mA
Input Leakage IIL-1.0 +1.0 μA
I/O Leakage IOL (Note 5) -1.0 +1.0 μA
Input Current IMOT (Note 6) -1.0 +500 μA
Output Current at 2.4V IOH (Note 2) -1.0 mA
Output Current at 0.4V IOL (Note 2) 4.0 mA
-332.7 2.882.97Power-Fail Voltage (Note 2) VPF-54.054.334.5V
-33 VRT Trip Point VRTTRIP-5 1.3 V
Trickle-Charger Current-Limiting
Resistor R1 DS12R885 Only10k
Trickle-Charger Output Voltage VOUT DS12R885 Only 3.05 V
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
DC ELECTRICAL CHARACTERISTICS (DS12R885 Only)(VCC
= 0V, VBACKUP= 3.2V, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS VBACKUP Current (OSC On);
TA = +25°C, VBACKUP = 3.0V IBACKUP2 (Note 7) 800 1000 nA
VBACKUP Current (Oscillator Off) IBACKUPDR (Note 7) 100 nA
AC ELECTRICAL CHARACTERISTICS(VCC = 4.5V to 5.5V, TA = -40°C to +85°C, (DS12R887-33 and DS12R887-5, TA = -20°C to +60°C.)) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS Cycle Time tCYC180 DC ns
Pulse Width, DS Low or R/WPWEL80 ns
Pulse Width, DS High or R/WPWEH65 ns
Input Rise and Fall tR, tF 30 ns
R/W Hold Time tRWH0 ns
R/W Setup Time Before DS/E tRWS10 ns
Chip-Select Setup Time Before
DS or R/WtCS5 ns
Chip-Select Hold Time tCH0 ns
Read-Data Hold Time tDHR5 35 ns
Write-Data Hold Time tDHW0 ns
Address Valid Time to AS Fall tASL20 ns
Address Hold Time to AS Fall tAHL5 ns
Delay Time DS/E to AS Rise tASD10 ns
Pulse Width AS High PWASH30 ns
Delay Time, AS to DS/E Rise tASED35 ns
Output Data Delay Time from DS
or R/WtDDR (Note 8)1560 ns
Data Setup Time tDSW50 ns
Reset Pulse Width tRWL5 μs
IRQ Release from DS tIRDS0 2 μs
IRQ Release from RESETtIRR02 μs
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 3.63V, TA = -40°C to +85°C, (DS12R887-33 and DS12R887-5, TA = -20°C to +60°C.)) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS Cycle Time tCYC280 DC ns
Pulse Width, DS Low or R/W High PWEL130 ns
Pulse Width, DS High or R/W Low PWEH90 ns
Input Rise and Fall tR, tF 30 ns
R/W Hold Time tRWH0 ns
R/W Setup Time Before DS tRWS15 ns
Chip-Select Setup Time Before
DS or R/WtCS8 ns
Chip-Select Hold Time tCH0 ns
Read-Data Hold Time tDHR5 55 ns
Write-Data Hold Time tDHW0 ns
Address Valid Time to AS Fall tASL30 ns
Address Hold Time to AS Fall tAHL15 ns
Delay Time DS to AS Rise tASD15 ns
Pulse Width AS High PWASH45 ns
Delay Time, AS to DS Rise tASED55 ns
Output Data Delay Time from DS
or R/WtDDR (Note 8)2080 ns
Data Setup Time tDSW70 ns
Reset Pulse Width tRWL5 μs
IRQ Release from DS tIRDS02 μs
IRQ Release from RESETtIRR02 μs
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle ChargerPWASH
PWEL
tASED
tCYC
tRWS
tCS
tRWH
tCH
PWEH
tASD
AD0–AD7
READ
R/W
AD0–AD7
WRITE
tDHW
tDHR
tDDR
tAHLtASL
tDSW
Motorola Bus Read/Write Timing
Intel Bus Write TimingPWASH
PWELPWEH
tCS
tAHLtASLtDSWtDHW
tCH
tASD
tASD
tCYC
R/W
AD0–AD7
WRITE
tASED
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle ChargertCS
tAHLtASL
tCYC
PWASH
PWELPWEH
R/W
AD0–AD7
tASD
tASD
tASED
tDDRtDHR
tCH
Intel Bus Read TimingtRWL
tIRR
tIRDS
RESET
IRQ
IRQRelease Delay Timing OUTPUTS
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZEDRECOGNIZED
VALID
VCC
VPF(MAX)
VPF(MIN)
tDR
tRPU
Power-Up/Power-Down Timing
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
POWER-UP/POWER-DOWN CHARACTERISTICS(TA = -40°C to +85°C, (DS12R887-33 and DS12R887-5, TA = -20°C to +60°C.)) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRecovery at Power-UptRPU20200ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)tF300µs
VCC Rise Time; VPF(MIN) to
VPF(MAX)tR0µs
CAPACITANCE(TA= +25°C)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCapacitance on All Input Pins
Except X1 and X2 CIN (Note 9) 10 pF
Capacitance on IRQ, SQW, and
DQ Pins CIO (Note 9) 10 pF
DATA RETENTION (DS12CR887)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSExpected Data Retention tDR TA = +25°C 5 Years
TESTCONDITIONS
PARAMETERTEST CONDITIONSInput Pulse Levels (-5)0 to 3.0V
Input Pulse Levels (-33)0 to 2.7V
Output Load Including Scope and Jig (-5)50pF + 1TTL Gate
Output Load Including Scope and Jig (-33)25pF + 1TTL Gate
Input and Output Timing Measurement Reference LevelsInput/Output: VIL maximum and VIH minimum
Input-Pulse Rise and Fall Times5ns
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1:Limits at -40°C are guaranteed by design and not production tested.
Note 2:All voltages are referenced to ground.
Note 3:All outputs are open.
Note 4:Specified with CS= DS = R/W= RESET= VCC; MOT, AS, AD0–AD7 = 0; VBACKUPopen.
Note 5:Applies to the AD0 to AD7 pins, the IRQpin, and the SQW pin when each is in a high-impedance state.
Note 6:The MOT pin has an internal 20kΩpulldown.
Note 7:Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8:Measured with a 50pF capacitance load.
Note 9:Guaranteed by design. Not production tested.
Typical Operating Characteristics (VCC= +3.3V, TA= +25°C, unless otherwise noted.)
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGEDS12R885 toc04
SUPPLY (V)
FREQUENCY (Hz)
IBACKUP vs. TEMPERATURE
(DS12R885)
DS12R885 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (nA)50-25-1052035
VCC = 0V,
VBACKUP = 3.0V
VBACKUP vs. VCC vs. IBACKUP
(DS12R885)DS12R885 toc02
VCC (V)
BACKUP
(V)
0μA
-15μA
-30μA
-45μA
-60μA
IBACKUP vs. VBACKUP
(DS12R885)DS12R885 toc01
VBACKUP (V)
SUPPLY CURRENT (nA)
VCC = 0V
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle ChargerPOWER
CONTROL
AND
TRICKLE
CHARGER
VBACKUP
OSC
BUS
INTERFACE
VCC
DS12R887/
DS12CR887
ONLY
DS12R887/
DS12CR887
ONLY
RESET
R/W
MOT
AD0–AD7
DIVIDE
BY 8
DIVIDE
BY 64
DIVIDE
BY 64
16:1 MUX
SQUARE-
WAVE
GENERATOR
REGISTERS A, B, C, D
CLOCK/CALENDAR AND
ALARM REGISTERS
USER RAM
114 BYTES
CLOCK/CALENDAR
UPDATE LOGIC
IRQ
SQW
IRQ
GENERATOR
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
GND
RLCR
DS12R885
Functional Diagram
Pin Description
PIN
SO EDIP BGANAME FUNCTION 1 1 C5 MOT
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left
disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor.
2 — — X1
3 — — X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a 12.5pF specified load capacitance (CL).
Pin X1 is the input to the oscillator and can optionally be connected to an external
32.768kHz oscillator. The output of the internal oscillator, pin X2, is left unconnected if
an external oscillator is connected to pin X1.
4–11 4–11
F4, D4,
F3, D3,
F2, D2,
F1, D1
AD0–
AD7
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first
portion of the bus cycle and latched into the DS12R885 by the falling edge of AS. Write
data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel
timing). In a read cycle, the DS12R885 outputs data during the latter portion of DS (DS and
R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is
terminated and the bus returns to a high-impedance state as DS transitions low in the case
of Motorola timing or as DS transitions high in the case of Intel timing.
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
Pin Description (continued)
PIN
SO EDIP BGANAME FUNCTION 12, 16 12
D5–D8,
E1–E8,
F5–F8
GND Ground
13 13 C1 CS
Chip-Select Input. The active-low chip-select signal must be asserted low for a bus cycle
in the DS12R885 to be accessed. CS must be kept in the active state during DS and AS
for Motorola timing and during DS and R/W for Intel timing. Bus cycles that take place
without asserting CS latch addresses, but no access occurs. When VCC is below VPF volts,
the DS12R885 inhibits access by internally disabling the CS input. This action protects the
RTC data and the RAM data during power outages.
14 14 C3 AS
Address Strobe Input. A positive-going address-strobe pulse serves to demultiplex the
bus. The falling edge of AS causes the address to be latched within the DS12R885. The
next rising edge that occurs on the AS bus clears the address regardless of whether CS is
asserted. An address strobe must immediately precede each write or read access. If a
write or read is performed with CS deasserted, another address strobe must be performed
prior to a read or write access with CS asserted.
15 15 C2 R/W
Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level that indicates whether the current
cycle is a read or write. A read cycle is indicated with a high level on R/W while DS is high.
A write cycle is indicated when R/W is low during DS. When the MOT pin is connected to
GND for Intel timing, the R/W signal is an active-low signal. In this mode, the R/W pin
operates in a similar fashion as the write-enable signal (WE) on generic RAMs. Data are
latched on the rising edge of the signal. 2, 3, 16,
20–22 A3 N.C. No Connection. This pin should remain unconnected. On the EDIP, these pins are missing
by design.
17 17 A1 DS
Data Strobe or Read Input. The DS pin has two modes of operation depending on the level of
the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this
mode, DS is a positive pulse during the latter portion of the bus cycle and is called data
strobe. During read cycles, DS signifies the time that the DS12R885 is to drive the
bidirectional bus. In write cycles, the trailing edge of DS causes the DS12R885 to latch the
written data. When the MOT pin is connected to GND, Intel bus timing is selected. DS
identifies the time period when the DS12R885 drives the bus with read data. In this mode, the
DS pin operates in a similar fashion as the output-enable (OE) signal on a generic RAM.
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
Pin Description (continued)
PIN
SO EDIP BGANAME FUNCTION 18 18 A2 RESET
Reset Input. The active-low RESET pin has no effect on the clock, calendar, or RAM. On
power-up, the RESET pin can be held low for a time to allow the power supply to
stabilize. The amount of time that RESET is held low is dependent on the application.
However, if RESET is used on power-up, the time RESET is low should exceed 200ms to
ensure that the internal timer that controls the DS12R885 on power-up has timed out.
When RESET is low and VCC is above VPF, the following occurs:
A. Periodic interrupt-enable (PIE) bit is cleared to 0.
B. Alarm interrupt-enable (AIE) bit is cleared to 0.
C. Update-ended interrupt-enable (UIE) bit is cleared to 0.
D. Periodic-interrupt flag (PF) bit is cleared to 0.
E. Alarm-interrupt flag (AF) bit is cleared to 0.
F. Update-ended interrupt flag (UF) bit is cleared to 0.
G. Interrupt-request status flag (IRQF) bit is cleared to 0.
H. IRQ pin is in the high-impedance state.
I. The device is not accessible until RESET is returned high.
J. Square-wave output-enable (SQWE) bit is cleared to 0.
In a typical application, RESET can be connected to VCC. This connection allows the
DS12R885 to go in and out of power fail without affecting any of the control registers.
19 19 A4 IRQ
Interrupt Request Output. The IRQ pin is an active-low output of the DS12R885 that can
be used as an interrupt input to a processor. The IRQ output remains low as long as the
status bit causing the interrupt is present and the corresponding interrupt-enable bit is
set. The processor program normally reads the C register to clear the IRQ pin. The
RESET pin also clears pending interrupts. When no interrupt conditions are present, the
IRQ level is in the high-impedance state. Multiple interrupting devices can be
connected to an IRQ bus, provided that they are all open drain. The IRQ pin is an open-
drain output and requires an external pullup resistor to VCC.
20 — — VBACKUP
Connection for Rechargeable Battery or Super Cap. This pin provides trickle charging
when VCC is greater than VBACKUP. On the DS12CR887 and DS12R887, the VBACKUP pin
is missing and is internally connected to a lithium cell.
21 — A5 RCLR
RAM Clear. The active-low RCLR pin is used to clear (set to logic 1) all 114 bytes of
general-purpose RAM, but does not affect the RAM associated with the RTC. To clear
the RAM, RCLR must be forced to an input logic 0 during battery-backup mode when
VCC is not applied. The RCLR function is designed to be used through a human
interface (shorting to ground manually or by a switch) and not to be driven with external
buffers. This pin is internally pulled up. Do not use an external pullup resistor on this
pin.
23 23 C4 SQW
Square-Wave Output. The SQW pin can output a signal from one of 13 taps provided by
the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed
by programming Register A, as shown in Table 3. The SQW signal can be turned on and
off using the SQWE bit in Register B. The SQW signal is not available when VCCis less
than VPF.
24 24
A6–A8,
B1–B8,
C6–C8
VCC
DC Power Pin for Primary Power Supply. When VCC is applied within normal limits, the
device is fully accessible and data can be written and read. When VCC is below VPF
reads and writes are inhibited.
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
Detailed DescriptionThe DS12R885 is a drop-in replacement for the
DS12885 RTC. The device provides 14 bytes of real-
time clock/calendar, alarm, and control/status registers
and 114 bytes of nonvolatile, battery-backed static
RAM. A time-of-day alarm, three maskable interrupts
with a common interrupt output, and a programmable
square-wave output are available. The DS12R885 also
operates in either 24-hour or 12-hour format with an
AM/PM indicator. A precision temperature-compensat-
ed circuit monitors the status of VCC. If a primary
power-supply failure is detected, the device automati-
cally switches to a backup supply. The backup supply
input supports either a rechargeable battery or a super
cap, and includes an integrated trickle charger. The
trickle charger is always enabled. The DS12R885 is
accessed through a multiplexed address/data bus that
supports Intel and Motorola modes.
The DS12R887 is a surface-mount package using the
DS12R885 die, a 32.768kHz crystal, and a recharge-
able battery. The device provides a real-time clock/cal-
endar, one time-of-day alarm, three maskable interrupts
with a common interrupt output, a programmable
square wave, and 114 bytes of nonvolatile, battery-
backed static RAM. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including correction for leap years. It also oper-
ates in either 24-hour or 12-hour format with an AM/PM
indicator. A precision temperature-compensated circuit
monitors the status of VCC. If a primary power failure is
detected, the device automatically switches to a back-
up battery included in the package. The device is
accessed through a multiplexed byte-wide interface,
which supports both Intel and Motorola modes.
The DS12CR887 EDIP integrates a DS12R885 die with
a crystal and battery. The charging circuit on the
DS12R885 die is disabled. The battery has sufficient
capacity to power the oscillator and registers for five
years in the absence of VCCat +25°C.
The DS12R887 BGA includes a crystal and a recharge-
able battery. A fully charged battery can power the oscil-
lator and registers (typical current at +25°C) in the
absence of VCCfor approximately 11 days (10% of
capacity consumed) or 98 days (90% capacity con-
sumed). When the discharge depth is 10% of capacity,
the battery can be recharged up to 1,000 times. If the dis-
charge depth is 90% of capacity, the battery can be
recharged up to 30 times. Thus, the life of the device
would be approximately 30 years (11 days X 1,000
cycles) or 8 years (98 days x 30 cycles). Charging time to
full capacity is approximately two days with VCCapplied.
Please consult related application notes for detailed
information on battery lifetime versus depth of dis-
charge, and expected product lifetime based upon
battery cycles.
Oscillator CircuitThe DS12R885 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 1 specifies several crys-
tal parameters for the external crystal. Figure 1 shows a
functional schematic of the oscillator circuit. An enable
bit in the control register controls the oscillator.
Oscillator startup times are highly dependent upon
crystal characteristics, PC board leakage, and layout.
High ESR and excessive capacitive loads are the major
contributors to long startup times. A circuit using a
crystal with the recommended characteristics and
proper layout usually starts within one second.
COUNTDOWN
CHAINX2
CRYSTAL
CL1CL2RTC REGISTERS
DS12R885
Figure 1. Oscillator Circuit Showing Internal Bias Network
PARAMETERSYMBOLMINTYPMAXUNITSNominal
Frequency fO 32.768 kHz
Series
Resistance ESR 50 k
Load
Capacitance CL 12.5 pF
Table 1. Crystal Specifications**The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks (RTCs)for
additional specifications.