DS1305EN ,Serial Alarm Real Time Clock (RTC)PIN DESCRIPTIONV - Primary Power SupplyCC1V - Backup Power SupplyCC2V - +3V Battery InputBATV - Int ..
DS1305EN ,Serial Alarm Real Time Clock (RTC)FEATURES PIN ASSIGNMENT Real time clock counts seconds, minutes,V 120VCC2 CC1hours, date of the mo ..
DS1305EN+ ,Serial Alarm Real-Time ClockFEATURES PIN ASSIGNMENT Real-time clock (RTC) counts seconds,V 120VCC2 CC1minutes, hours, date of ..
DS1305EN+T , Serial Alarm Real-Time Clock
DS1305EN+T , Serial Alarm Real-Time Clock
DS1305N ,Serial Alarm Real Time Clock (RTC)FEATURES PIN ASSIGNMENT Real time clock counts seconds, minutes,V 120VCC2 CC1hours, date of the mo ..
DTC115TUA , 100mA / 50V Digital transistors (with built-in resistors)
DTC123EE ,Bias Resistor TransistorELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)ACharacteristic Symbol Min ..
DTC123EET1 ,Bias Resistor TransistorFeatures(OUTPUT)PIN 1R1• Simplifies Circuit DesignBASE(INPUT)• Reduces Board SpaceR2• Reduces Compo ..
DTC123EET1 ,Bias Resistor TransistorMAXIMUM RATINGS (T = 25°C unless otherwise noted)ASC−75/SOT−416CASE 463xx MRating Symbol Value Un ..
DTC123J ,Bias Resistor TransistorMaximum ratings are those values beyond which device damage can occur.See specific marking informat ..
DTC123JCA ,Conductor Holdings Limited - Digital Transistor
DS1305E-DS1305EN-DS1305N
Serial Alarm Real Time Clock (RTC)
FEATURESReal time clock counts seconds, minutes,
hours, date of the month, month, day of the
week and year with leap year compensationvalid up to 210096-byte nonvolatile RAM for data storageTwo time-of-day alarms programmable on
combination of seconds, minutes, hours and
day of the weekSerial interface supports Motorola serial
peripheral interface (SPI) serial data ports or
standard 3-wire interfaceBurst mode for reading/writing successive
addresses in clock/RAMDual power supply pins for primary and
backup power suppliesOptional trickle charge output to backup
supply2.0 - 5.5V operationOptional industrial temperature range
-40°C to +85°CAvailable in space-efficient, 20-pin TSSOP
packageRecognized by Underwriters Laboratory
ORDERING INFORMATIONDS1305 16-Pin DIP
DS1305N 16-Pin DIP (Industrial)
DS1305E 20-Pin TSSOPDS1305EN 20-Pin TSSOP (Industrial)
PIN ASSIGNMENT
DS1305
Serial Alarm Real Time Clock (RTC)
DS1305
PIN DESCRIPTIONVCC1- Primary Power Supply
VCC2 - Backup Power Supply
VBAT - +3V Battery Input
VCCIF - Interface Logic Power Supply Input
GND - GroundX1, X2 - 32.768 kHz Crystal Connection
INT0 - Interrupt 0 Output
INT1 - Interrupt 1 Output
SDI - Serial Data In
SDO - Serial Data Out
CE - Chip Enable
SCLK - Serial ClockSERMODE - Serial Interface Mode - Power Fail Output
DESCRIPTIONThe DS1305 Serial Alarm Real Time Clock provides a full BCD clock calendar which is accessed via a
simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month and year
information. The end of the month date is automatically adjusted for months with less than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with
AM/PM indicator. In addition 96 bytes of nonvolatile RAM are provided for data storage.
An interface logic power supply input pin (VCCIF) allows the DS1305 to drive SDO and PF pins to a level
that is compatible with the interface logic. This allows an easy interface to 3-volt logic in mixed supply
systems.
The DS1305 offers dual power supplies as well as a battery input pin. The dual power supplies support aprogrammable trickle charge circuit which allows a rechargeable energy source (such as a super cap or
rechargeable battery) to be used for a backup supply. The VBAT pin allows the device to be backed up by
a non-rechargeable battery. The DS1305 is fully operational from 2.0 to 5.5 volts.
Two programmable time of day alarms are provided by the DS1305. Each alarm can generate aninterrupt on a programmable combination of seconds, minutes, hours and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. The time of
day alarms can be programmed to assert two different interrupt outputs or to assert one common interrupt
output. Both interrupt outputs operate when the device is powered by VCC1, VCC2, or VBAT.
The DS1305 supports a direct interface to Motorola SPI serial data ports or standard 3-wire interface. A
straightforward address and data format is implemented in which data transfers can occur 1 byte at a time
or in multiple-byte burst mode.
OPERATIONThe block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The following
paragraphs describe the function of each pin.
DS1305
DS1305 BLOCK DIAGRAM Figure 1
SIGNAL DESCRIPTIONS
VCC1 - DC power is provided to the device on this pin. VCC1 is the primary power supply.
VCC2 - This is the secondary power supply pin. In systems using the trickle charger, the rechargeable
energy source is connected to this pin.
VBAT - Battery input for any standard 3-volt lithium cell or other energy source.
VCCIF (Interface Logic Power Supply Input) - The VCCIF pin allows the DS1305 to drive SDO and PF
out-put pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3-volt
logic in mixed supply systems. This pin is physically connected to the source connection of the p-channel
transistors in the output buffers of the SDO and PF pins.
SERMODE (Serial Interface Mode Input) - The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication isselected. When connected to VCC, Motorola SPI communication is selected.
SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface foreither the SPI or 3-wire interface.
SDI (Serial Data Input) - When SPI communication is selected, the SDI pin is the serial data input forthe SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).
SDO (Serial Data Output) - When SPI communication is selected, the SDO pin is the serial data outputfor the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI
DS1305
CE (Chip Enable) - The Chip Enable signal must be asserted high during a read or a write for both 3-wire and SPI communication. This pin has an internal 55K pull-down resistor (typical).
INT0(Interrupt 0 Output) - The INT0 pin is an active low output of the DS1305 that can be used as an
interrupt input to a processor. The INT0 pin can be programmed to be asserted by only Alarm 0 or can be
programmed to be asserted by either Alarm 0 or Alarm 1. The INT0 pin remains low as long as the status
bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0 pin
operates when the DS1305 is powered by VCC1, VCC2, or VBAT. The INT0 pin is an open drain output and
requires an external pull-up resistor.
INT1(Interrupt 1 Output) - The INT1 pin is an active low output of the DS1305 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1 only. The
INT1 pin remains low as long as the status bit causing the interrupt is present and the corresponding
interrupt enable bit is set. The INT1 pin operates when the DS1305 is powered by VCC1, VCC2, or VBAT.
The INT1 pin is an open drain output and requires an external pull-up resistor.
Both INT0and INT1are open drain outputs. The two interrupts and the internal clock continue to run
regardless of the level of VCC (as long as a power source is present).
(Power Fail Output) - The PF pin is used to indicate loss of the primary power supply (VCC1).
When VCC1 is less than VCC2 or is less than VBAT , the PF pin will be driven low.
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator is designed foroperation with a crystal having a specified load capacitance of 6 pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
with Dallas Real Time Clocks.” The DS1305 can also be driven by an external 32.768 kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
DS1305
RTC AND RAM ADDRESS MAPThe address map for the RTC and RAM registers of the DS1305 is shown in Figure 2. Data is written to
the RTC by writing to address locations 80h to 9Fh and is written to the RAM by writing to address
locations A0h to FFh. RTC data is read by reading address locations 00h to 1Fh and RAM data is read by
reading address locations 20h to 7Fh.
ADDRESS MAP Figure 2
CLOCK, CALENDAR AND ALARMThe time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time, calendar and alarm are set or initialized by writing
the appropriate register bytes. Note that some bits are set to zero. These bits will always read 0
regardless of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh arereserved. These registers will always read 0 regardless of how they are written. The contents of the time,
calendar and alarm registers are in the binary-coded decimal (BCD) format.
Please note that the initial power on state of all registers in not defined. Therefore it is important to
enable the oscillator (EOSC = 0) and disable write protect (WP = 0) during initial configuration.
DS1305
RTC REGISTERS Figure 3
RTC Registers DS1305Alarm 1
Range For Alarm Registers Does Not Include Mask’m’ Bits.
The DS1305 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1305 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to registers
87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. The alarms can be
programmed (by the INTCN bit of the Control Register) to operate in two different modes - each alarm
can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 ofeach of the time of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a
time of day alarm will only occur once per week when the values stored in timekeeping registers 00h to
03h match the values stored in the time of day alarm registers. An alarm will be generated every day
when bit 7 of the day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7
of the day and hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minutewhen bit 7 of the day, hour and minute alarm registers is set to a logic 1. When bit 7 of the day, hour,
minute and seconds alarm registers is set to a logic 1, alarm will occur every second.
DS1305
TIME OF DAY ALARM MASK BITS Table 1
SPECIAL PURPOSE REGISTERSThe DS1305 has three additional registers (Control Register, Status Register and Trickle Charger
Register) that control the real time clock, interrupts and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
EOSC(Enable oscillator) - This bit when set to logic 0 will start the oscillator. When this bit is set to alogic 1, the oscillator is stopped and the DS1305 is placed into a low-power standby mode with a current
drain of less than 100 nanoamps when power is supplied by VBAT or VCC2 . The initial power on state is
not defined.
WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. Whenhigh, the write protect bit prevents a write operation to any register, including bits 0, 1, 2 and 7 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.
INTCN (Interrupt Control) - This bit controls the relationship between the two time of day alarms andthe interrupt output pins. When the INTCN bit is set to a logic 1, a match between the timekeeping
registers and the Alarm 0 registers will activate the INT0 pin (provided that the alarm is enabled) and a
match between the timekeeping registers and the Alarm 1 registers will activate the INT1 pin (provided
that the alarm is enabled). When the INTCN bit is set to a logic 0, a match between the timekeeping
registers and either Alarm 0 or Alarm 1 will activate the INT0 pin (provided that the alarms are enabled).
INT1 has no function when INTCN is set to a logic 0.
AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag(IRQF0) bit in the status register to assert INT0
. When the AIE0 bit is set to logic 0, the IRQF0 bit doesnot initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag(IRQF1) bit in the status register to assert INT1 (when INTCN=1) or to assert INT0 (when INTCN=0).
When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal.
DS1305
STATUS REGISTER (READ 10H)
IRQF0 (Interrupt 0 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the currenttime has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin will go low.
IRQF0 is cleared when any of the Alarm 0 registers are read or written.
IRQF1 (Interrupt 1 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the currenttime has matched the Alarm 1 registers. This flag can be used to generate an interrupt on either INT0 or
INT1 depending on the status of the INTCN bit in the Control Register. If the INTCN bit is set to a logic
1 and IRQF1 is at a logic 1 (and AIE1 bit is also a logic 1), the INT1 pin will go low. If the INTCN bit is
set to a logic 0 and IRQF1 is at a logic 1 (and AIE1 bit is also a logic 1), the INT0 pin will go low.
IRQF1 is cleared when any of the Alarm 1 registers are read or written.
TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)This register controls the trickle charge characteristics of the DS1305. The simplified schematic of
Figure 4 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits4-7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of
1010 will enable the trickle charger. All other patterns will disable the trickle charger. The DS1305
powers up with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether one
diode or two diodes are connected between VCC1 and VCC2 . If DS is 01, one diode is selected. If DS is
10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independent of TCS. TheRS bits select the resistor that is connected between VCC1 and VCC2. The resistor is selected by the resister
select (RS) bits as shown in Table 2.
PROGRAMMABLE TRICKLE CHARGER Figure 4
DS1305
TRICKLE CHARGER RESISTOR SELECT Table 2If RS is 00, the trickle charger is disabled independent of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired forbattery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5 volts is applied to VCC1 and a super cap is
connected to VCC2 . Also assume that the trickle charger has been enabled with 1 diode and resister R1
between VCC1 and VCC2. The maximum current I MAX would therefore be calculated as follows:
I MAX = (5.0V - diode drop)/R1(5.0V - 0.7V)/2 kΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop between VCC1 and VCC2 will decrease and therefore
the charge current will decrease.
POWER CONTROLPower is provided through the VCC1, VCC2 and VBAT pins. Three different power supply configurations
are illustrated in Figure 5. Configuration 1 shows the DS1305 being backed up by a non-rechargeableenergy source such as a lithium battery. In this configuration, the system power supply is connected to
VCC1 and VCC2 is grounded. The DS1305 will be write protected if VCC1 is less than VBAT .
Configuration 2 illustrates the DS1305 being backed up by a rechargeable energy source. In this case, the
VBAT pin is grounded, VCC1 is connected to the primary power supply and VCC2 is connected to thesecondary supply (the rechargeable energy source). The DS1305 will operate from the larger of VCC1 or
VCC2. When VCC1 is greater than VCC2 + 0.2 volt (typical), VCC1 will power the DS1305. When VCC1 is
less than VCC2, VCC2 will power the DS1305. The DS1305 does not write protect itself in this
configuration.
Configuration 3 shows the DS1305 in battery operate mode where the device is powered only by a single
battery. In this case, the VCC1 and VBAT pins are grounded and the battery is connected to the VCC2 pin.
Only these three configurations are allowed. Unused supply pins must be grounded.
SERIAL INTERFACEThe DS1305 offers the flexibility to choose between two serial interface modes. The DS1305 cancommunicate with the SPI interface or with a standard 3-wire inter-face. The interface method used is
determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected.
DS1305
SERIAL PERIPHERAL INTERFACE (SPI)The serial peripheral interface (SPI) is a synchronous bus for address and data transfer and is used when
interfacing with the SPI bus on specific Motorola microcontrollers such as the 68HC05C4 and the
68HC11A8. The SPI mode of serial communication is selected by tying the SERMODE pin to VCC.
Four pins are used for the SPI. The four pins are the SDO (Serial Data Out), SDI (Serial Data In), CE
(Chip Enable) and SCLK (Serial Clock). The DS1305 is the slave device in an SPI application, with themicrocontroller being the master.
The SDI and SDO pins are the serial data input and output pins for the DS1305, respectively. The CE
input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data
movement between the master (microcontroller) and the slave (DS1305) devices.
The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data
transfer to any device on the SPI bus. The inactive clock polarity is programmable in some
microcontrollers. The DS1305 offers an important feature in that the level of the inactive clock is
determined by sampling SCLK when CE becomes active. Therefore either SCLK polarity can beaccommodated. Input data (SDI) is latched on the internal strobe edge and output data (SDO) is shifted
out on the shift edge (see Table 3 and Figure 6). There is one clock for each bit transferred. Address and
data bits are transferred in groups of eight.
POWER SUPPLY CONFIGURATIONS FOR THE DS1305 Figure 5
Configuration 1: Backup Supply is a Non-Rechargeable Lithium Battery
DS1305
Configuration 2: Backup Supply is a Rechargeable Battery or Super
Capacitor
Configuration 3: Battery Operate Mode
FUNCTION TABLE Table 3High ZCPOL is the “Clock Polarity” bit that is set in the control register of the microcontroller.
** SDO remains at High Z until 8 bits of data are ready to be shifted out during a read.
