DS90CF364MTD ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C363 transmitter converts 21 bits of CMOS/TTLdata ..
DS90CF364MTD/NOPB ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF364MTDX ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C363 transmitter converts 21 bits of CMOS/TTLdata ..
DS90CF364MTDX/NOPB ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkFEATURES DESCRIPTIONThe DS90C363 transmitter converts 21 bits of23• 20 to 65 MHz shift clock suppor ..
DS90CF366MTD ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85 MHzGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF386 receiver ..
DS90CF383AMTD ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz [Life-time buy]Featuresn 20 to 65 MHz shift clock supportThe DS90C383A/DS90CF383A transmitter converts 28 bitsof C ..
DS90C363MTD-DS90C363MTDX-DS90CF364MTD-DS90CF364MTDX
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz
DS90C363/DS90CF364
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link —65 MHz, +3.3V LVDS Receiver
18-Bit Flat Panel Display (FPD) Link— 65 MHz
General DescriptionThe DS90C363 transmitter converts21bitsof CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams.Aphase-locked transmit clock istransmittedin
parallelwiththe data streams over afourth LVDSlink. Every
cycleofthe transmit clock21bitsof input dataare sampled
and transmitted. The DS90CF364 receiver convertsthe
LVDS data streams backinto21bitsof CMOS/TTL data.At transmit clock frequencyof65 MHz,18bitsof RGB data
and3 bitsof LCD timing and control data (FPLINE,
FPFRAME,DRDY)are transmittedat arateof455 Mbpsper
LVDS data channel.Using a65 MHz clock,the data through-
putsis170 Mbytes/sec.The Transmitteris offeredwith pro-
grammable edgedata strobesfor convenient interfacewitha
varietyof graphics controllers.The Transmittercanbe pro-
grammedfor Rising edge strobeor Falling edge strobe
througha dedicatedpin.A Rising edge Transmitterwill inter-
operate witha Falling edge Receiver (DS90CF364) without
any translation logic.
This chipsetisan ideal meansto solve EMIand cable size
problems associated with wide, high speed TTL interfaces.
Features20to65 MHz shift clock support Programmable Transmitter (DS90C363) strobe select
(Risingor Falling edge strobe) Single 3.3V supply Chipset(Tx+Rx) power consumption< 250mW (typ) Power-down mode(<0.5mW total) Single pixelper clock XGA (1024x768) ready Supports VGA, SVGA, XGAand higher addressability.Upto170 Megabyte/sec bandwidthUpto1.3 Gbps throughput Narrowbus reduces cable sizeand cost 290mV swing LVDS devicesforlowEMI PLL requiresno external components Low profile 48-lead TSSOP package Falling edge data strobe Receiver Compatible with TIA/EIA-644 LVDS standard ESD rating> 7kV Operating Temperature: −40˚Cto +85˚C
Block DiagramsTRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
ApplicationDS012886-14
September 1999
DS90C363/DS90CF364
+3.3V
Programmable
VDS
18-Bit-Color
Flat
Panel
Display
(FPD)
Link
MHz©1999 National Semiconductor Corporation DS012886
