DS90CF383BMT ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHzBlock DiagramDS90C383B20098401Order Number DS90C383BMTSee NS Package Number MTD56®TRI-STATE is a re ..
DS90CF383BMTX/NOPB ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 56-TSSOP -10 to 70FEATURES DESCRIPTIONThe DS90CF383B transmitter converts 28 bits of23• No Special Start-up Sequence ..
DS90CF383MTD ,+ 3.3V LVDS 24-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF384AMTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF384A receiver ..
DS90CF384AMTD. ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF384AMTD/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkFEATURES DESCRIPTIONThe DS90CF384A receiver converts the four LVDS2• 20 to 65 MHz Shift Clock Suppo ..
DS90C383BMT-DS90C383BMT.-DS90C383BMTX-DS90CF383BMT
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90C383B
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-65 MHz
General DescriptionThe DS90C383B transmitter converts28 bitsof CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams.A phase-locked transmit clockis transmittedin
parallel with the data streams overa fifth LVDS link. Every
cycleofthe transmit clock28 bitsof input dataare sampled
and transmitted.Ata transmit clock frequencyof65 MHz,24
bitsof RGB data and3 bitsof LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmittedata rateof 455
Mbps per LVDS data channel. Usinga65 MHz clock, the
data throughputis 227 Mbytes/sec. The DS90C383B trans-
mitter canbe programmedfor Rising edge strobeor Falling
edge strobe througha dedicated pin.A Rising edgeor
Falling edge strobe transmitterwill interoperate witha Falling
edge strobe Receiver (DS90CF386) without any translation
logic.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
canbe applied either beforeor afterthe deviceis
powered. Support Spread Spectrum Clockingupto 100kHz
frequency modulation& deviationsof ±2.5% center
spreador −5% down spread. "Input Clock Detection" featurewill pullall LVDS pairsto
logic low when input clockis missing and when /PDpin logic high.18to68 MHz shift clock support Best–in–Class Set& Hold Timeson TxINPUTsTx power consumption< 130 mW (typ) @65MHz
Grayscale 40% Less Power Dissipation than BiCMOS AlternativesTx Power-down mode< 60µW (typ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow bus reduces cable size and cost Upto1.8 Gbps throughput Upto 227 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devicesfor low EMI PLL requiresno external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package Improved replacement for:
SN75LVDS83, DS90C383A
Block Diagram
DS90C383BOrder Number DS90C383BMT
See NS Package Number MTD56
PRELIMINARY
July 2004
DS90C383B
+3.3V
Programmable
VDS
ransmitter
24-Bit
Flat
Panel
Display
(FPD)
Link-65
