DS90CF388AVJD ,Dual Pixel LVDS Display Interface / FPD-Link ReceiverBlock Diagrams10132001 2DS90C387A/DS90CF388ADS90C387A/DS90CF388AAbsolute Maximum Ratings (Note 1) P ..
DS90CF388VJD ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAGeneral Descriptionreduce EMI and shielding requirements. For more details,The DS90C387/DS90CF388 t ..
DS90CF388VJDX ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAFeaturesdata into 8 LVDS (Low Voltage Differential Signalling) datan Complies with OpenLDI specific ..
DS90CF561MTD ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF561 transmitt ..
DS90CF561MTDX ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF561 transmitt ..
DS90CF562MTD ,LVDS 18-Bit Color Flat Panel Display (FPD) LinkFeaturesdata streams. A phase-locked transmit clock is transmitted inn Up to 105 Megabyte/sec bandw ..
DS90C387AVJD-DS90CF388AVJD
Dual Pixel LVDS Display Interface / FPD-Link Transmitter
DS90C387A/DS90CF388A
Dual Pixel LVDS Display Interface/ FPD-Link
General DescriptionThe DS90C387A/DS90CF388A transmitter/receiver pairis
designedto support dual pixel data transmission between
Host and Flat Panel Displayupto QXGA resolutions. The
transmitter converts 48 bits (Dual Pixel 24-bit color)of
CMOS/TTL data and3 control bits into8 LVDS (Low Voltage
Differential Signalling) data streams.Ata maximum dual
pixel rateof 112MHz, LVDS data line speedis 784Mbps,
providinga total throughputof 5.7Gbps (714 Megabytes per
second).
The LDI chipsetis improved over prior generationsof
FPD-Link devices and offers higher bandwidth support and
longer cable drive.To increase bandwidth, the maximum
pixel clock rateis increasedto 112 MHz and8 serialized
LVDS outputs are provided. Cable driveis enhanced witha
user selectable pre-emphasis feature that provides addi-
tional output current during transitionsto counteract cable
loading effects.
The DS90C387A transmitter providesa second LVDS output
clock. Both LVDS clocksare identical. This feature supports
backward compatibility with the previous generationof
FPD-Link Receivers- the second clock allowsthe transmit-
terto interfaceto panels usinga ’dual pixel’ configurationof
two 24-bitor 18-bit FPD-Link receivers.
This chipsetisan ideal meansto solve EMI and cable size
problemsfor high-resolution flat panel applications.It pro-
videsa reliable interface basedon LVDS technology that
delivers the bandwidth neededfor high-resolution panels
while maximizingbit times, and keeping clock rates lowto
reduce EMI and shielding requirements. For more details,
please refertothe “Applications Information” sectionof this
datasheet.
Features Supports SVGA through QXGA panel resolutions 32.5to 112/170MHz clock support Drives long, low cost cables Upto5.7 Gbps bandwidth Pre-emphasis reduces cable loading effects Dual pixel architecture supports interfaceto GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface Transmitter rejects cycle-to-cycle jitter5V toleranton data and control input pins Programmable transmitter data and control strobe select
(risingor falling edge strobe) Backward compatible with FPD-Link Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
Generalized Transmitter Block DiagramOctober 2002
DS90C387A/DS90CF388A
Dual
Pixel
VDS
Display
Interface
FPD-Link
