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Partno	Mfg	Dc	Qty	Available	Descript
DS90C387VJD	DS	N/a	3	avai	+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
DS90C387VJD/NOPB \|DS90C387VJDNOPB	NS Pb-free	N/a	360	avai	+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA 100-TQFP -10 to 70

DS90C387VJD/NOPB ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA 100-TQFP -10 to 70Maximum RatingsSupply Voltage (V )−0.3V to +4VCCCMOS/TTL Input Voltage−0.3V to +5.5VCMOS/TTL Output ..
DS90C387VJDX ,+3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGAapplications. Itn Compatible with ANSI/TIA/EIA-644-1995 LVDS Standardprovides a reliable interface ..
DS90c401 ,Dual Low Voltage Differential Signaling (LVDS) DriverElectrical CharacteristicsOver supply voltage and operating temperature ranges, unless otherwise sp ..
DS90C401M ,Dual Low Voltage Differential Signaling (LVDS) DriverFeaturesn Ultra low power dissipationThe DS90C401 is a dual driver device optimized for highdata ra ..
DS90C401M/NOPB ,Dual Low Voltage Differential Signaling (LVDS) Driver 8-SOIC FEATURES DESCRIPTIONThe DS90C401 is a dual driver device optimized for2• Ultra Low Power Dissipatio ..
DS90C401MX ,Dual Low Voltage Differential Signaling (LVDS) DriverElectrical CharacteristicsOver supply voltage and operating temperature ranges, unless otherwise sp ..

DS90C387VJD-DS90C387VJD/NOPB
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
DS90C387, DS90CF388
www.ti.com SNLS012H –MAY 2000–REVISED APRIL 2013
DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
Checkfor Samples: DS90C387, DS90CF388
1FEATURES DESCRIPTION
The DS90C387/DS90CF388 transmitter/receiver pair Complies with OpenLDI Specification for is designedto support dual pixel data transmissionDigital Display Interfaces between Host and Flat Panel Display upto QXGA• 32.5to 112/170MHz Clock Support for resolutions. The transmitter converts 48 bits (DualDS90C387,40to 112MHz Clock Support for Pixel 24-bit color)of CMOS/TTL data into8 LVDS
DS90CF388 (Low Voltage Differential Signalling) data streams.
Control signals (VSYNC, HSYNC, DE and two user-• Supports SVGA through QXGA Panel defined signals) are sent during blanking intervals.AtResolutions a maximum dual pixel rateof 112MHz, LVDS data• Drives Long, Low Cost Cables line speedis 672Mbps, providinga total throughputof Upto 5.38Gbps Bandwidth 5.38Gbps (672 Megabytes per second). Two other
modes are also supported. 24-bit color data (single• Pre-Emphasis Reduces Cable Loading Effects pixel) can be clocked into the transmitter ata• DC Balance Data Transmission Providedby maximum rate of 170MHz. In this mode, theTransmitter Reduces ISI Distortion transmitter provides single-to-dual pixel conversion, Cable Deskewof +/−1 LVDS Data Bit Time (up and the output LVDS clock rateis 85MHz maximum.80 MHz Clock Rate)of Pair-to-Pair Skewat The third mode provides inter-operability with FPD-
Link devices.Receiver Inputs; Intra-Pair Skew Toleranceof
300ps The LDI chipsetis improved over prior generationsof Dual Pixel Architecture Supports Interfaceto FPD-Link devices and offers higher bandwidth
GUI and Timing Controller; Optional Single support and longer cable drive with three areasof
enhancement. To increase bandwidth, the maximumPixel Transmitter Inputs Support Single Pixel
pixel clock rateis increasedto 112 (170) MHz and8GUI Interface serialized LVDS outputs are provided. Cable driveis• Transmitter Rejects Cycle-to-Cycle Jitter enhanced with a user selectable pre-emphasis• 5V Tolerant on Data and Control Input Pins feature that provides additional output current during
transitionsto counteract cable loading effects. DC• Programmable Transmitter Data and Control balancing ona cycle-to-cycle basis,is also providedStrobe Select (Risingor Falling Edge Strobe) to reduce ISI (Inter-Symbol Interference). With pre-• Backward Compatible Configuration Select emphasis and DC balancing,a low distortion eye-with FPD-Link patternis providedat the receiver endof the cable.A Clock for Backward cable deskew capability has been addedto deskew long cablesof pair-to-pair skewof upto +/−1 LVDS
databit time (upto 80 MHz Clock Rate). These three enhancements allow cables 5+ metersin lengthto be Balanced Mode driven. This chipsetis an ideal meansto solve EMI LVDS for high-resolution flat panel applications.It providesa reliable interface based on
LVDS technology bandwidth needed
for high-resolution
and keeping clock rates low to reduce
shielding requirements. For more details, please Applications Information.

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