DS90CF363BMT ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF363BMT ,+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkGeneral Descriptionlogic low when input clock is missing and when /PD pinTheDS90CF363Btransmitterco ..
DS90CF363MTD ,+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz [Life-time buy]Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF364AMTD ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesbandwidth) back into parallel 28 bits of CMOS/TTL data (24n 20 to 65 MHz shift clock suppor ..
DS90CF364AMTDX ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHzDS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit-Color Flat Panel Display (FPD)Link—65 MHz , +3.3V ..
DS90CF364AMTDX/NOPB ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkElectrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CF363BMT
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link
DS90CF363B
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link -65 MHz
General DescriptionThe DS90CF363B transmitterconverts21 bitsof CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. Aphase-locked transmit clockis transmittedin
parallel withthe data streams overa fourth LVDS link. Every
cycleofthe transmit clock21 bitsof input dataare sampled
and transmitted.Ata transmit clock frequencyof65 MHz,18
bitsof RGB data and3 bitsof LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmittedata rateof 455
Mbps per LVDS data channel. Usinga65 MHz clock, the
data throughputis 170 Mbytes/sec. The DS90CF363Bis
fixedasa Falling edge strobe transmitter andwill interoper-
ate witha Falling edge strobe Receiver (DS90CF366) with-
out any translation logic.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
canbe applied either beforeor afterthe deviceis
powered. Support Spread Spectrum Clockingupto 100KHz
frequency modulation& deviationsof ±2.5% center
spreador −5% down spread. "Input Clock Detection" featurewill pullall LVDS pairsto
logic low when input clockis missing and when /PDpin logic high.18to68 MHz shift clock support Best–in–Class Set& Hold Timeson TxINPUTsTx power consumption< 130 mW (typ) @65MHz
Grayscale 40% Less Power Dissipation than BiCMOS AlternativesTx Power-down mode< 37µW (typ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow bus reduces cable size and cost Upto1.3 Gbps throughput Upto 170 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devicesfor low EMI PLL requiresno external components Compatible with TIA/EIA-644 LVDS standard Low profile 48-lead TSSOP package Improved replacement for:
SN75LVDS84, DS90CF363A
Block Diagram
DS90CF363BOrder Number DS90CF363BMT
See NS Package Number MTD48
PRELIMINARY
July 2004
+3.3V
Programmable
VDS
ransmitter
18-Bit
Flat
Panel
Display
(FPD)
Link
MHz
