DS90CF386MTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF386MTDX NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkBlock Diagrams. 174 Revision HistoryNOTE: Page numbers for previous revisions may differ from page ..
DS90CF386MTDX/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkFeatures 3 DescriptionThe DS90CF386 receiver converts four LVDS (Low1• 20-MHz to 85-MHz Shift Clock ..
DS90CF386SLC ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzBlock DiagramsDS90CF386 DS90CF3661010852710108528Order Number DS90CF386MTD or DS90CF386SLCOrder Num ..
DS90CF386SLCX/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link SNLS055J–NOVEMBER 1999–REVISED MAY 20165 Pin Configuration and FunctionsDGG Package48-Pin TSSOPTop ..
DS90CF388AVJD ,Dual Pixel LVDS Display Interface / FPD-Link ReceiverBlock Diagrams10132001 2DS90C387A/DS90CF388ADS90C387A/DS90CF388AAbsolute Maximum Ratings (Note 1) P ..
DS90CF366MTD-DS90CF386MTD-DS90CF386MTDX-DS90CF386SLC
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85 MHz
DS90CF386/DS90CF366
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link — 85 MHz, +3.3V L VDS Receiver 18-Bit Flat Panel
Display (FPD) Link—85 MHz
General DescriptionThe DS90CF386 receiver converts the four LVDS data
streams (Upto 2.38 Gbps throughputor 297.5 Megabytes/
sec bandwidth) back into parallel28 bitsof CMOS/TTL data
(24 bitsof RGB and4 bitsof Hsync, Vsync, DE and CNTL).
Also availableis the DS90CF366 that converts the three
LVDS data streams (Upto 1.78 Gbps throughputor 223
Megabytes/sec bandwidth) back into parallel 21 bitsof
CMOS/TTL data(18 bitsof RGB and3 bitsof Hsync, Vsync
and DE). Both Receivers’ outputs are Falling edge strobe.A
Rising edgeor Falling edge strobe transmitter (DS90C385/
DS90C365)will interoperate witha Falling edge strobe Re-
ceiver without any translation logic.
The DS90CF386is also offeredina64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which providesa44%
reductionin PCB footprint comparedto the 56L TSSOP
package.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features20to85 MHz shift clock supportRx power consumption <142 mW (typ) @85MHz
GrayscaleRx Power-down mode <1.44 mW (max) ESD rating>7kV (HBM), >700V (EIAJ) Supports VGA, SVGA, XGA and Single Pixel SXGA. PLL requiresno external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-leador 48-lead TSSOP package DS90CF386 also availableina64 ball, 0.8mm fine pitch
ball grid array (FBGA) package
Block Diagrams
DS90CF386 DS90CF366Order Number DS90CF386MTDor DS90CF386SLC
SeeNS Package Number MTD56or SLC64A
Order Number DS90CF366MTD
SeeNS Package Number MTD48
May 2003
DS90CF386/DS90CF366
+3.3V
VDS
Receiver
24-Bit-Color
Flat
Panel
Display
(FPD)
Link
MHz,
+3.3V
VDS
Receiver
18-Bit-Color
Flat
Panel
Display
(FPD)
Link
MHz
