DS90CR215MTDX/NOPB ,+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel LinkFEATURES DESCRIPTIONThe DS90CR215 transmitter converts 21 bits of2• Single +3.3V SupplyCMOS/TTL dat ..
DS90CR216 ,+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel LinkFeaturesparallel with the data streams over a fourth LVDS link. Everyn Single +3.3V supplycycle of ..
DS90CR216 ,+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel LinkBlock DiagramsDS90CR215 DS90CR216DS012909-1DS012909-27Order Number DS90CR215MTDOrder Number DS90CR2 ..
DS90CR216AMTD ,+3.3V Rising Edge Data Strobe LVDS Receiver 21-Bit Channel Link-66 MHzFeaturesn 20 to 66 MHz shift clock supportThe DS90CR286A receiver converts the four LVDS datastream ..
DS90CR216AMTDX ,+3.3V Rising Edge Data Strobe LVDS Receiver 21-Bit Channel Link-66 MHzElectrical Characteristics (Continued)Over recommended operating supply and temperature ranges unle ..
DS90CR216MTD ,+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel LinkFeaturesparallel with the data streams over a fourth LVDS link. Everyn Single +3.3V supplycycle of ..
DS90CR215MTDX/NOPB
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link
DS90CR215, DS90CR216
www.ti.com SNLS129D –MARCH 1999–REVISED APRIL 2013
DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS
21-Bit Channel Link- 66 MHz
Checkfor Samples: DS90CR215, DS90CR216
1FEATURES DESCRIPTIONThe DS90CR215 transmitter converts 21 bits of
Single +3.3V Supply CMOS/TTL data into three LVDS (Low Voltage
• Chipset (Tx+ Rx) Power Consumption <250 Differential Signaling) data streams.A phase-locked
mW (typ) transmit clockis transmittedin parallel with the data
Power-down Mode (<0.5 mW total) streams overa fourth LVDS link. Every cycleof the
transmit clock 21 bitsof input data are sampled and
• Upto 173 Megabytes/sec Bandwidth transmitted. The DS90CR216 receiver converts the
• Upto 1.386 Gbps Data Throughput LVDS data streams back into 21 bitsof CMOS/TTL
Narrow Bus Reduces Cable Size data.Ata transmit clock frequencyof66 MHz,21 bits TTL data are transmittedata rateof 462 Mbps per
• 290 mV Swing LVDS Devices for Low EMI LVDS data channel. Usinga 66 MHz clock, the data
• +1V Common Mode Range (Around +1.2V) throughputis 1.386 Gbit/s (173 Mbytes/s).
• PLL Requires No External Components The multiplexing of the data lines provides a
• Low Profile 48-Lead TSSOP Package substantial cable reduction. Long distance parallel
Rising Edge Data Strobe single-ended buses typically requirea ground wire
per active signal (and have very limited noise
• Compatible with TIA/EIA-644 LVDS Standard rejection capability). Thus, fora 21-bit wide data and
• ESD Rating>7 kV one clock,upto 44 conductors are required. With the
• Operating Temperature: −40°Cto +85°C Channel Link chipsetas fewas9 conductors(3 data
pairs,1 clock pair anda minimumof one ground) are
needed. This providesa 80% reductionin required
cable width, which providesa system cost savings,
reduces connector physical size and cost, and
reduces shielding requirements dueto the cables'
smaller form factor.
The 21 CMOS/TTL inputs can supporta varietyof
signal combinations. For example, five 4-bit nibbles
plus1 control, or two 9-bit (byte+ parity) and3
control.
Figure2. DS90CR216- Improved AC Specifications See Package Number DGG0048A