DS90CR283MTD ,28-Bit Channel-LinkBlock DiagramsDS90CR283 DS90CR284DS012889-27 DS012889-1Order Number DS90CR283MTD Order Number DS90C ..
DS90CR284MTD ,28-Bit Channel-LinkFeaturesLVDS data streams back into 28 bits of CMOS/TTL data. Ata transmit clock frequency of 66 MH ..
DS90CR285MTD ,+3.3V Rising Edge Data Strobe LVDS 28-Bit ChannelGeneral Descriptionsignal combinations. For example, seven 4-bit nibbles orThe DS90CR285 transmitte ..
DS90CR286AMTD ,+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CR286AMTDX ,+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHzDS90CR286A/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit ChannelLink—66 MHz, +3.3V ..
DS90CR286MTD ,+3.3V Rising Edge Data Strobe LVDS 28-Bit ChannelGeneral Descriptionsignal combinations. For example, seven 4-bit nibbles orThe DS90CR285 transmitte ..
DS90CR283MTD-DS90CR284MTD
28-Bit Channel-Link
DS90CR283/DS90CR284
28-Bit Channel Link-66 MHz
General DescriptionThe DS90CR283 transmitter converts28 bitsof CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams.A phase-locked transmit clockis transmittedin
parallel with the data streams overa fifth LVDS link. Every
cycleofthe transmit clock28 bitsof input dataare sampled
and transmitted. The DS90CR284 receiver converts the
LVDS data streams back into28 bitsof CMOS/TTL data.At transmit clock frequencyof66 MHz,28 bitsof TTL dataare
transmittedata rateof 462 Mbps per LVDS data channel.
Usinga66 MHz clock, the data throughputis 1.848 Gbit/s
(231 Mbytes/s).
The multiplexingof the data lines providesa substantial
cable reduction. Long distance parallel single-ended buses
typically requirea ground wire per active signal (and have
very limited noise rejection capability). Thus,fora 28-bitwide
data bus and one clock,upto58 conductors are required.
With the Channel Link chipsetas fewas11 conductors(4
data pairs,1 clock pair anda minimumof one ground) are
needed. This providesa 80% reductionin required cable
width, which providesa system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments dueto the cables’ smaller form factor.
The28 CMOS/TTL inputs can supporta varietyof signal
combinations. For example,7 4-bit nibblesor3 9-bit (byte+
parity) and1 control.
Features66 MHz clock support Upto 231 Mbytes/s bandwidth Low power CMOS design(< 610 mW) Power Down mode(< 0.5 mW total) Upto 1.848 Gbit/s data throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devicesfor low EMI PLL requiresno external components Low profile 56-lead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
DS90CR283DS012889-27
Order Number DS90CR283MTD
SeeNS Package Number MTD56
DS90CR284DS012889-1
Order Number DS90CR284MTD
SeeNS Package Number MTD56July 2001
DS90CR283/DS90CR284
28-Bit
Channel
Link-66
MHz
