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DS90CR485VS/NOPB
133MHz LVDS 48-bit Channel Link Serializer 100-TQFP -10 to 70
DS90CR485
www.ti.com SNLS143D–FEBRUARY 2003–REVISED MARCH 2013
DS90CR485 133MHz 48-bit Channel Link Serializer (6.384 Gbps)
Checkfor Samples: DS90CR485
1FEATURES DESCRIPTIONThe DS90CR485 serializes the 24 LVCMOS/LVTTL
Upto 6.384 Gbps Throughput double edge inputs (48 bits data latchedin per clock
• 66MHzto 133MHz Input Clock Support cycle) onto8 Low Voltage Differential Signaling
Reduces Cable and Connector Size and Cost (LVDS) streams.A phase-locked transmit clockis
alsoin parallel with the data streams overa 9th
• Pre-Emphasis Reduces Cable Loading Effects LVDS link. The reductionof the wide TTL bustoa
• DC Balance Reduces ISI Distortion few LVDS lines reduces cable and connector size
• 24 Bit Double Edge Inputs and cost. The double edge input strobes data on both
the rising and falling edges of the clock. This
• 3V Tolerant LVCMOS/LVTTL Inputs minimizes the pin count required and simplifies PCB
• Low Power, 2.5V Supply routing between the host chip and the serializer.
• Flow-Through Pinout This chipis an ideal solution to solve EMI and
• In 100-Pin TQFP Package interconnect size problems for high throughput point-
• Conforms with TIA/EIA-644-A LVDS Standard to-point applications.
The DS90CR485 is intended for use with the
DS90CR486 Channel-Link receiver. It is also
backward compatible with other Channel-Link
receiver suchas the DS90CR482 and DS90CR484.
For more details, please refer to the Applications
Information sectionof this datasheet.
Generalized Block Diagram
