MAX3799ETJ+ ,1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driverapplications.♦ -21.5dBm Optical Sensitivity at 1.25Gbps Using aBy providing a selectable data path ..
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersMAX378/MAX37919-1902; Rev 1; 8/94High-Voltage, Fault-ProtectedAnalog Multiplexers_______________
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersApplicationsMAX378MJE -55°C to +125°C 16 CERDIPData Acquisition SystemsMAX378MLP -55°C to +125°C 20 ..
MAX379CPE ,High-Voltage, Fault-Protected Analog MultiplexersApplicationsMAX378MJE -55°C to +125°C 16 CERDIPData Acquisition SystemsMAX378MLP -55°C to +125°C 20 ..
MAX379CPE+ ,8-Channel, High-Voltage, Fault-Protected MultiplexersFeatures' Fault Input Voltage ±75V with Power Supplies OffThe MAX378 8-channel single-ended (1-of-8 ..
MAX379CWG ,High-Voltage, Fault-Protected Analog MultiplexersGeneral Description ________
MAX737CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM Regulatorsfeatures, along with
high efficiency and an application circuit that lends itself to
miniaturizat ..
MAX737CWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorslVI/lXI/VI
-5V, -12V, -15V, and Adjustable
Inverting Gurrent-Mode PWM Regulators
MAX737CWE+T ,-12V, Inverting, PWM, Current-Mode DC-DC ConverterELECTRICAL CHARACTERISTICS
Bootstrapped Mode (Circuit of Figure 1, V+ = w, ILOAD = 0mA, DRV- = V ..
MAX737EPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsELECTRICAL CHARACTERISTICS
Bootstrapped Mode (Circuit of Figure 1, V+ = w, ILOAD = 0mA, DRV- = V ..
MAX7381AXR166+T ,3-Pin Silicon OscillatorApplicationsPART TEMP RANGE PIN-PACKAGEWhite GoodsMAX7381AXR106-T -40°C to +125°C 3 SC70-3Automotiv ..
MAX7384CRUK ,10 MHz, 2.7 V to 5.5 V, silicon oscillator with low-power frequency switching and reset outputfeatures a factory-programmed high-speed♦ Integrated PORoscillator, a 32.768kHz oscillator, a clock ..
MAX3799ETJ+
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL DriverEVALUATION KIT AVAILABLE
General DescriptionThe MAX3799 is a highly integrated limiting amplifier
and VCSEL driver that operates up to 14Gbps, making
it suitable for Ethernet and Fibre Channel applications.
By providing a selectable data path with a noise-shap-
ing filter, the MAX3799 enables a module with 10G
optics to be fully compliant with both 1000BASE-SR
and 10GBASE-SR specifications. Operating from a sin-
gle +3.3V supply, this low-power integrated limiting
amplifier and VCSEL driver IC enables a platform
design for SFP MSA as well as for SFP+ MSA-based
optical transceivers. The high-sensitivity limiting ampli-
fier limits the differential input signal generated by a
transimpedance amplifier into a CML-level differential
output signal. The compact VCSEL driver provides a
modulation and a bias current for a VCSEL diode. The
optical average power is controlled by an average
power control (APC) loop implemented by a controller
that interfaces to the VCSEL driver through a 3-wire
digital interface. All differential I/Os are optimally back-
terminated for a 50Ωtransmission line PCB design.
The use of a 3-wire digital interface reduces the pin
count while enabling advanced Rx (rate selection, LOS
threshold, LOS squelch, LOS polarity, CML output level,
signal path polarity, deemphasis, and fast mode-select
change time) and Tx settings (modulation current, bias
current, polarity, and eye safety control) without the
need for external components. The MAX3799 provides
multiple current and voltage DACs to allow the use of
low-cost controller ICs.
The MAX3799 is packaged in a lead-free, 5mm x 5mm,
32-pin TQFN package.
Applications1000BASE-SR/10GBASE-SR Multirate SFP+
Optical Transceiver
1x/2x/4x/8x/16x SFF/SFP/SFP+ MSA Fibre
Channel (FC) Optical Transceiver
FeaturesEnables Single-Module Design Compliance with
1000BASE-SR and 10GBASE-SR Specifications-21.5dBm Optical Sensitivity at 1.25Gbps Using a
10.32Gbps ROSA (-19.7dBm OMA)Low Power Dissipation of 320mW at 3.3V Power
SupplyTypical Electrical Performance of 14.025Gbps on
Rx/Tx (Non-Retimed 16x Fibre Channel Solution)3mVP-PReceiver Sensitivity at 10.32Gbps4psP-PDJ at Receiver Output at 8.5Gbps 8B/10B4psP-PDJ at Receiver Output at 10.32Gbps
231- 1 PRBS26ps Rise and Fall Time at Rx/Tx OutputRate Select for 1Gbps Mode or 10Gbps ModeCML Output SquelchPolarity Select for Rx and TxLOS Assert Level AdjustmentLOS Polarity SelectModulation Current Up to 12mA Into 100Ω
Differential LoadBias Current Up to 15mAIntegrated Eye Safety Features3-Wire Digital InterfaceProgrammable Deemphasis at Tx Output
Ordering Information+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE MAX3799ETJ+ -40°C to +85°C 32 TQFN-EP*
Typical Application Circuit and Pin Configuration appear at
end of data sheet.
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out-
put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, VCC= 3.3V, IBIAS= 6mA, IMOD= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCR, VCCT, VCCD.................................................-0.3V to +4.0V
Voltage Range at DISABLE, SDA, SCL, CSEL,
RSEL, FAULT, BMON, LOS, CAZ2.........-0.3V to (VCC+ 0.3V)
Voltage Range at ROUT+, ROUT-.....(VCC- 1V) to (VCC+ 0.3V)
Voltage at TIN+, TIN-........................(VCC- 2.5V) to (VCC- 0.5V)
Voltage Range at TOUT+, TOUT-......(VCC- 2V) to (VCC+ 0.3V)
Voltage at BIAS............................................................0V to VCC
Voltage at RIN+, RIN-..........................(VCC- 2V) to (VCC- 0.2V)
Current Range into FAULT, LOS...........................-1mA to +5mA
Current Range into SDA........................................-1mA to +1mA
Current into ROUT+, ROUT-...............................................40mA
Current into TOUT+, TOUT-................................................60mA
Continuous Power Dissipation (TA= +70°C)
32-Pin TQFN (derate 34.5W/°C above +70°C)...........2759mW
Operating Junction Temperature Range...........-55°C to +150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY Power-Supply Current ICC
Includes the CML output current;
excludes IBIAS = 6mA, IMOD = 6mA,
VDIFF_ROUT = 400mVP-P (Note 1)
97 150 mA
Power-Supply Voltage VCC 2.85 3.63 V
GENERAL Input Data Rate 1.0625 10.32 Gbps
Input/Output SNR 14.1
BER 10E-12
POWER-ON RESET High POR Threshold 2.55 2.75 V
Low POR Threshold IBIAS = IBIASOFF and IMOD = IMODOFF 2.3 2.45 V
Rx INPUT SPECIFICATIONS Differential Input Resistance
RIN+/RIN- RIN_DIFF 75 100 125
RATE_SEL = 0 (1.25Gbps) 1 3 Input Sensitivity (Note 2) VINMINRATE_SEL = 1 (10.32Gbps) 3 8 mVP-P
Input Overload VINMAX 1.2 VP-P
DUT is powered on, f 5GHz 14Input Return Loss SDD11 DUT is powered on, f 16GHz 7dB
DUT is powered on, 1GHz < f 5GHz8Input Return Loss SCC11 DUT is powered on, 1GHz < f 16GHz8dB
Rx OUTPUT SPECIFICATIONS Differential Output Resistance ROUTDIFF 75 100 125
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out-
put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, VCC= 3.3V, IBIAS= 6mA, IMOD= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DUT is powered on, f 5GHz 11 Output Return Loss SDD22 DUT is powered on, f 16GHz 5 dB
DUT is powered on, 1GHz < f 5GHz 9 Output Return Loss SCC22 DUT is powered on, 1GHz < f 16GHz 7 dB
CML Differential Output Voltage
High 5mVP-P VIN 1200mVP-P, SET_CML[162] 595 800 1005 mVP-P
CML Differential Output Voltage
Medium 10mVP-P VIN 1200mVP-P, SET_CML[80] 300 400 515 mVP-P
CML Differential Output DAC
Limit SET_CML[7:0] 215
Differential Output Signal When
Disabled
Outputs AC-coupled, VINMAX applied to
input VDIFF_ROUT = 800mVP-P at 8.5Gbps
(Notes 2, 3)
6 15 mVP-P
10mVP-P VIN 1200mVP-P,
RATE_SEL = 1, VDIFF_ROUT = 400mVP-P 26 35 Data Output Transition Time
(20% to 80%)
(Notes 2, 3, 4)
tR/tF
5mVP-P VIN 1200mVP-P,
RATE_SEL = 0, VDIFF_ROUT = 800mVP-P 60 100
ps
Rx TRANSFER CHARACTERISTICS 60mVP-P VIN 400mVP-P at 10.32Gbps,
RATE_SEL = 1, VDIFF_ROUT = 400mVP-P 4 12
10mVP-P VIN 1200mVP-P at 8.5Gbps,
RATE _SEL = 1, VDIFF_ROUT = 400mVP-P 4 12 Deterministic Jitter
(Notes 2, 3, 5) DJ
5mVP-P VIN 1200mVP-P at 1.25Gbps,
RATE _SEL = 0, VDIFF_ROUT = 800mVP-P 20
psP-P
Input = 60mVP-P at 1.25Gbps,
RATE_SEL = 0, VDIFF_ROUT = 800mVP-P 1.82.5
Random Jitter (Notes 2, 3) RJ
Input = 60mVP-P at 8.5Gbps,
RATE _SEL = 1, VDIFF_ROUT = 400mVP-P 0.320.48
psRMS
CAZ = 0.1µF 2Low-Frequency Cutoff CAZ = open 500kHz
Rx LOS SPECIFICATIONS LOS Assert Sensitivity Range 14 77 mVP-P
LOS Hysteresis 10 x log(VDEASSERT/VASSERT) (Note 6) 1.25 2.1 dB
LOS Assert/Deassert Time (Note 7) 2.3 80 µs
Low Assert Level SET_LOS[7] (Notes 2, 6) 8 1114 mVP-P
Low Deassert Level SET_LOS[7] (Notes 2, 6) 14 18 21mVP-P
Medium Assert Level SET_LOS[32] (Notes 2, 6) 39 48 58mVP-P
Medium Deassert Level SET_LOS[32] (Notes 2, 6) 65 81 95mVP-P
High Assert Level SET_LOS[63] (Notes 2, 6) 77 94 112mVP-P
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out-
put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, VCC= 3.3V, IBIAS= 6mA, IMOD= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Tx INPUT SPECIFICATIONS Data rate = 1.0625Gbps 0.2 2.4 Differential Input Voltage VINData rate = 10.32Gbps 0.075 0.8 VP-P
Common-Mode Input Voltage VINCM 2.75 V
Differential Input Resistance RIN 75100 125
DUT is powered on, f 5GHz 15Input Return Loss SDD11 DUT is powered on, f 16GHz 6dB
DUT is powered on, 1GHz < f 5GHz 9Input Return Loss SCC11 DUT is powered on, 1GHz < f 16GHz 5dB
Tx LASER MODULATOR Maximum Modulation-On
Current into 100 Differential
Load
IMODMAX Outputs AC-coupled, VCCTO 2.95V 12 mA
Minimum Modulation-On Current
into 100 Differential Load IMODMIN Outputs AC-coupled 2 mA
Modulation Current DAC
Stability 2mA IMOD 12mA (Note 8) 4 %
Modulation Current Rise Time/
Fall Time tR/tF5mA IMOD 10mA, 20% to 80%,
SET_TXDE[3:0] = 10 (Notes 2, 4) 26 39 ps
5mA IMOD 12mA, at 10.32Gbps,
250mVP-P VIN 800mVP-P,
SET_TXDE[3:0] = 0
6 12
5mA IMOD 12mA, at 10.32Gbps,
250mVP-P VIN 800mVP-P,
SET_TXDE[3:0] = 10
6 13
5mA IMOD 12mA, at 8.5Gbps,
250mVP-P VIN 800mVP-P,
SET_TXDE[3:0] = 0
6 12
5mA IMOD 12mA, at 8.5Gbps,
250mVP-P VIN 800mVP-P,
SET_TXDE[3:0] = 10
6 12
2mA IMOD 12mA, at 4.25Gbps 5
Deterministic Jitter (Notes 2, 9) DJ
2mA IMOD 12mA, at 1.0625Gbps 5
ps
Random Jitter 5mA IMOD 12mA, 250mVP-P VIN
800mVP-P 0.17 0.5 psRMS
DUT is powered on, f 5GHz 12 Output Return Loss SDD22 DUT is powered on, f 16GHz 5 dB
Tx BIAS GENERATOR Maximum Bias-On Current IBIASMAX Current into BIAS pin 15 mA
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out-
put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, VCC= 3.3V, IBIAS= 6mA, IMOD= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIAS Current DAC Stability 2mA IBIAS 15mA (Notes 2, 10) 4 %
Compliance Voltage at BIAS VBIAS 0.9 2.1 V
BIAS Current Monitor Current
Gain IBMONExternal resistor to GND defines the
voltage gain 16 mA/A
Compliance Voltage at BMON VBMON 0 1.8 V
BIAS Current Monitor Current
Gain Stability IBMON 2mA IBIAS 15mA (Note 10) 5 %
Tx SAFETY FEATURES Excessive Voltage at BMON VBMON
Average voltage, FAULT warning always
occurs for VBMON VCC - 0.55V, FAULT
warning never occurs for VBMON VCC -
0.65V
VCC -
0.65V
VCC -
0.6V
VCC -
0.55V V
Excessive Voltage at BIAS VBIAS
Average voltage, FAULT always occurs for
VBIAS 0.44V, FAULT never occurs for
VBIAS 0.65V
0.44 0.48 0.65 V
Maximum VCSEL Current in Off
State IOFF FAULT or DISABLE, VBIAS = VCC 25 µA
SFP TIMING REQUIREMENTS DISABLE Assert Time t_OFF
Time from rising edge of DISABLE input
signal to IBIAS = IBIASOFF and IMOD =
IMODOFF 1 µs
DISABLE Negate Time t_ON
Time from falling edge of DISABLE to IBIAS
and IMOD at 90% of steady state when
FAULT = 0 before reset 500 µs
FAULT Reset Time of Power-On
Time t_INITTime from power-on or negation of FAULT
using DISABLE 100 ms
FAULT Reset Time t_FAULTTime from fault to FAULT on,
CFAULT 20pF, RFAULT = 4.7k 10 µs
DISABLE to Reset Time DISABLE must be held high to reset
FAULT 5 µs
OUTPUT_LEVEL VOLTAGE DAC (SET_CML) Full-Scale Voltage VFS 100 differential resistive load 1200 mVP-P
Resolution 5 mVP-P
Integral Nonlinearity INL 5mA ICML_LEVEL 20mA ±0.9 LSB
LOS THRESHOLD VOLTAGE DAC (SET_LOS) Full-Scale Voltage VFS 94 mVP-P
Resolution 1.5 mVP-P
Integral Nonlinearity INL 11mVP-P VTH_LOS 94mVP-P ±0.7 LSB
BIAS CURRENT DAC (SET_IBIAS) Full-Scale Current IFS21 mA
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out-
put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, VCC= 3.3V, IBIAS= 6mA, IMOD= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution 40 µA
Integral Nonlinearity INL 1mA IBIAS 15mA ±1 LSB
Differential Nonlinearity DNL 1mA IBIAS 15mA, guaranteed mono-
tonic at 8-bit resolution (SET_IBIAS[8:1]) ±1LSB
MODULATION CURRENT DAC (SET_IMOD) Full-Scale Current IFS21 mA
Resolution 40 µA
Integral Nonlinearity INL 2mA IMOD 12mA ±1 LSB
Differential Nonlinearity DNL 2mA IMOD 12mA, guaranteed mono-
tonic at 8-bit resolution (SET_IMOD[8:1]) ±1LSB
CONTROL I/O SPECIFICATIONS RSEL Input Current IIH, IIL 150 µA
RSEL Input High Voltage VIH 1.8 VCC V
RSEL Input Low Voltage VIL 0 0.8 V
RSEL Input Impedance RPULL Internal pulldown resistor 40 75 110 k
IIH 12 DISABLE Input Current IIL Dependency on pullup resistance 420 800 µA
DISABLE Input High Voltage VIH 1.8 VCC V
DISABLE Input Low Voltage VIL 0 0.8 V
DISABLE Input Impedance RPULL Internal pullup resistor 4.7 8 10 k
LOS, FAULT Output High Voltage VOH RLOS = 4.7k - 10k to VCC,
RFAULT = 4.7k - 10kto VCC
VCC -
0.5 VCC V
LOS, FAULT Output Low Voltage VOL RLOS = 4.7k - 10k to VCC,
RFAULT = 4.7k - 10kto VCC0 0.4 V
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL) Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL 0.8 V
Input Hysteresis VHYST 0.082 V
Input Leakage Current IIL, IIHVIN = 0V or VCC; internal pullup or pulldown
(75k typ) 150 µA
Output High Voltage VOH External pullup of 4.7k to VCCVCC -
0.5 V
Output Low Voltage VOL External pullup of 4.7k to VCC 0.4 V
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (See Figure 4) SCL Clock Frequency fSCL 400 1000 kHz
SCL Pulse-Width High tCH 0.5 µs
SCL Pulse-Width Low tCL 0.5 µs
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out-
put load is AC-coupled to differential 100Ω(see Figure 1), typical values are at +25°C, VCC= 3.3V, IBIAS= 6mA, IMOD= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SDA Setup Time tDS 100 ns
SDA Hold Time tDH 100 ns
SCL Rise to SDA Propagation
Time tD 5ns
CSEL Pulse-Width Low tCSW 500 ns
CSEL Leading Time Before the
First SCL Edge tL500 ns
CSEL Trailing Time After the
Last SCL Edge tT500 ns
SDA, SCL External Load CBTotal bus capacitance on one line with
4.7k pullup to VCC 20 pF
Note 1:Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-
put and the bias current output must be connected to a separate supply to remove the modulation/bias current portion from
the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ωload resistors to a separate
supply voltage.
Note 2:Guaranteed by design and characterization, TA= -40°C to +95°C.
Note 3:The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-
istic jitter caused by this filter is not included in the DJ generation specifications.
Note 4:Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1.
Note 5:Receiver deterministic jitter is measured with a repeating 231- 1 PRBS equivalent pattern at 10.32Gbps. For 1.25Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6:Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 231- 1 PRBS at 10.32Gbps.
Note 7:Measurement includes an input AC-coupling capacitor of 100nF and CCAZof 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload.
Signal_OFF = 0
Signal_ON = 1.2VP-P
max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.
Note 8:Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC
from +2.95V to +3.63V. Reference current measured at VCC= +3.2V, TA= +25°C.
Note 9:Transmitter deterministic jitter is measured with a repeating 27- 1 PRBS, 72 0s, 27- 1 PRBS, and 72 1s pattern at
10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is
defined as the arithmetic sum of PWD and PDJ.
Note 10:Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCCfrom +2.85V to +3.63V. Reference current measured at VCC= +3.3V, TA= +25°C.
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL DriverMAX3799
VCCR
LOS
RSEL
ROUT+
DISABLE
VCCD
VEER
VEET
FAULT
TOUT+
VCCT
BIAS
1nF
0.1µF
0.1µF
1000pF
50Ω
50Ω
4.7kΩ
4.7kΩ
1kΩ
1000pF
1µH
VCC
VCCR
VCCT
VCCD
0.1µF
0.1µF
VCCR
VCCT
VCCD
1000pF
VCCT
OSCILLOSCOPE
VCCR
CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
50Ω
ROUT-
0.1µF
50Ω
50Ω
SCLSDACSELTIN+
0.1µF
TIN-BMON
CAZ1CAZ2
RIN+
0.1µF
RIN-
TOUT-
0.1µF
50Ω
OSCILLOSCOPE
50Ω
50Ω
0.1µF0.1µF
Figure 1. Test Circuit for VCSEL Driver Characterization
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Typical Operating Characteristics—Limiting Amplifier(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
RANDOM JITTER
vs. INPUT AMPLITUDEMAX3799 toc01
INPUT AMPLITUDE (mVP-P)
RANDOM JITTER (ps)
RATE_SEL = 1
DETERMINISTIC JITTER vs.
INPUT AMPLITUDE AT 1.25GbpsMAX3799 toc02
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER (ps)
PATTERN = k28.5, RATE_SEL = 0
DETERMINISTIC JITTER
vs. INPUT AMPLITUDEMAX3799 toc03
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER (ps)
PATTERN = PRBS, RATE_SEL = 1
AT 8.5Gbps
AT 10.32Gbps
DETERMINISTIC JITTER
vs. DATA RATEMAX3799 toc04
DATA RATE (Gbps)
DETERMINISTIC JITTER (ps)102468
RATE_SEL = 1
PATTERN = k28.5
BER vs. INPUT AMPLITUDEMAX3799 toc05
INPUT AMPLITUDE (mVP-P)
BER
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
1.0E-13
1.0E-12
RATE_SEL = 0
RATE_SEL = 1
OUTPUT EYE DIAGRAM AT 1.25GbpsMAX3799 toc06
200ps/div
150mV/div
RATE_SEL = 0
OUTPUT EYE DIAGRAM AT 4.25GbpsMAX3799 toc07
50ps/div
50mV/div
RATE_SEL = 1
OUTPUT EYE DIAGRAM AT 8.5GbpsMAX3799 toc08
20ps/div
50mV/div
OUTPUT EYE DIAGRAM AT 10.32GbpsMAX3799 toc09
20ps/div
50mV/div
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Typical Operating Characteristics—Limiting Amplifier (continued)(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
OUTPUT EYE DIAGRAM AT 14.025GbpsMAX3799 toc10
20ps/div
50mV/div
RATE_SEL = 1, RXDE_EN = 1
TRANSITION TIME
vs. INPUT AMPLITUDEMAX3799 toc11
INPUT AMPLITUDE (mVP-P)
TRANSITION TIME (ps)
PATTERN = 00001111
20% TO 80%
RATE_SEL = 0, RXDE_EN = 0
RATE_SEL = 1, RXDE_EN = 0
RATE_SEL = 1, RXDE_EN = 1
LOS THRESHOLD vs. DAC SETTINGMAX3799 toc12
SET_LOS[5:0]
LOS THRESHOLD (mV)4935421421287
DEASSERT
ASSERT
SENSITIVITY vs. DATA RATEMAAX3799 toc13
DATA RATE (Gbps)
SENSITIVITY OMA (dBm)753
RATE_SEL = 1
RATE_SEL = 0
USING FINISAR ROSA
Rx INPUT RETURN LOSSMAX3799 toc14
FREQUENCY (Hz)
SDD11 (dB)
10G1G
100M100G
Rx OUTPUT RETURN LOSSMAX3799 toc15
FREQUENCY (Hz)
SDD22 (dB)
10G1G
100M100G
CML OUTPUT AMPLITUDE
vs. DAC SETTINGMAX3799 toc16
CML OUTPUT AMPLITUDE (mV
P-P
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX3799 toc17
SUPPLY CURRENT (mA)653550-10520-25
IBIAS = 12mA
IBIAS = 9mA
IBIAS = 2mA
IMOD = 2mA; RECEIVER OUTPUT = 400mVP-P;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1
TOTAL SUPPLY CURRENT
vs. TEMPERATUREMAX3799 toc18
SUPPLY CURRENT (mA)653550-10520-25
IMOD = 12mA
IMOD = 9mA
IMOD = 2mA
IBIAS = 2mA; RECEIVER OUTPUT = 400mVP-P;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driverypical Operating Characteristics—VCSEL Driver (continued)(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
OPTICAL EYE DIAGRAMMAX3799 toc19
68ps/div
2.125Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 50%
OPTICAL EYE DIAGRAMMAX3799 toc20
34ps/div
4.25Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 46%
OPTICAL EYE DIAGRAMMAX3799 toc21
17ps/div
8.5Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 54%
OPTICAL EYE DIAGRAMMAX3799 toc22
14ps/div
10.3Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 44%
ELECTRICAL EYE DIAGRAMMAX3799 toc23
14ps/div
14.025Gbps, SET_IMOD = 60, 231 - 1 PRBS
EYE WIDTH
62.8ps
DETERMINISTIC JITTER
vs. MODULATION CURRENTMAX3799 toc24
MODULATION CURRENT (mAP-P)
DETERMINISTIC JITTER (ps)864
PATTERN = PRBS, DATA RATE = 10.32Gbps
TRANSITION TIME
vs. MODULATION CURRENTMAX3799 toc25
TRANSITION TIME (ps)864
FALL TIME
RISE TIME
PATTERN = 11110000,
DATA RATE = 8.5Gbps
TRANSITION TIME
vs. DEEMPHASIS SETTINGMAX3799 toc26
TRANSITION TIME (ps)912356748
FALL TIME
RISE TIME
PATTERN = 11110000,
DATA RATE = 8.5Gbps,
IMOD = 10mAP-P
MODULATION CURRENT
vs. DAC SETTINGMAX3799 toc27
MODULATION CURRENT (mA)
RLOAD = 50Ω
RLOAD = 75Ω
RLOAD = 100Ω
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driverypical Operating Characteristics—VCSEL Driver (continued)(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
BIAS CURRENT
vs. DAC SETTINGMAX3799 toc28
SET_IBIAS[8:0]
BIAS CURRENT (mA)
TRANSMITTER DISABLE
MAX3799 toc29
100ns/div
VCC
FAULT
DISABLE
OUTPUT
LOW
LOW
HIGH
3.3V
TRANSMITTER ENABLEMAX3799 toc30
1μs/div
VCC
FAULT
DISABLE
OUTPUT
LOW
LOW
HIGH
3.3V
tON = 420ns
RESPONSE TO FAULTMAX3799 toc31
1μs/div
VBIAS
FAULT
DISABLE
OUTPUT
LOW
LOW
HIGH
EXTERNALLY
FORCED FAULT
FAULT RECOVERYMAX3799 toc32
4μs/div
VBIAS
FAULT
DISABLE
OUTPUT
LOW
LOW
HIGH
EXTERNAL
FAULT
HIGH
FREQUENCY ASSERTION OF DISABLEMAX3799 toc33
4μs/div
VBIAS
FAULT
DISABLE
OUTPUT
LOW
LOW
HIGH
HIGH
EXTERNALLY
FORCED FAULT
Tx INPUT RETURN LOSSMAX3799 toc34
SDD11 (dB)
10G1G
100M100G
Tx OUTPUT RETURN LOSSMAX3799 toc35
SDD22 (dB)
10G1G
100M100G
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Pin Description
PINNAMEFUNCTION1 LOS
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
2 RSEL
Mode-Select Input, TTL/CMOS. Set the RSEL pin or RATE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting RSEL and RATE_SEL logic-low for high-gain mode.
The RSEL pin is internally pulled down by a 75k resistor to ground.
3, 6, 27, 30 VCCR Power Supply. Provides supply voltage to the receiver block. ROUT+ Noninverted Receive Data Output, CML. Back-terminated for 50 load. ROUT- Inverted Receive Data Output, CML. Back-terminated for 50 load.
7 VCCD Power Supply. Provides supply voltage for the digital block.
8 DISABLE Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k resistor to VCCT.SCL Serial-Clock Input, TTL/CMOS. This pin has a 75kinternal pulldown.
10 SDA
Serial-Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k internal pullup,
but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
11 CSEL
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internally pulled down by a 75k resistor to
ground.
12, 15, 18,
21, 24, 25 VCCT Power Supply. Provides supply voltage to the transmitter block.
ypical Operating Characteristics—VCSEL Driver (continued)(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
DETERMINISTIC JITTER
vs. PULSE-WIDTH SETTINGMAX3799 toc36
SET_PWCTRL[3:0]
DETERMINISTIC JITTER (ps)3-5-3-117
PATTERN = PRBS, DATA RATE = 10.32Gbps
EYE CROSSING
DOWNUP
BIAS MONITOR CURRENT
vs. TEMPERATUREMAX3799 toc37
TEMPERATURE (°C)
MONITOR CURRENT (65-25-105352050
IBIAS = 12mA
IBIAS = 8mA
IBIAS = 2mA
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Detailed DescriptionThe MAX3799 SFP+ transceiver combines a limiting
amplifier receiver with loss-of-signal detection and a
VCSEL laser driver transmitter with fault protection.
Configuration of the advanced Rx and Tx settings of the
MAX3799 is performed by a controller through the
3-wire interface. The MAX3799 provides multiple cur-
rent and voltage DACs to allow the use of low-cost con-
troller ICs.
Limiting Amplifier ReceiverThe limiting amplifier receiver inside the MAX3799 is
designed to operate from 1.0625Gbps to 10.32Gbps.
The receiver includes a dual path limiter, offset correc-
tion circuitry, CML output stage with deemphasis, and
loss-of-signal circuitry. The functions of the receiver can
be controlled through the on-chip 3-wire interface. The
registers that control the receiver functionality are
RXCTRL1, RXCTRL2, RXSTAT, MODECTRL, SET_CML,
and SET_LOS.
Pin Description (continued)
PINNAMEFUNCTION14 TIN- Inverted Transmit Data Input, CML
16 BMON Bias Current Monitor Output. Current out of this pin develops a ground-referenced voltage across an
external resistor that is proportional to the laser bias current.
17 VEET Ground. Provides ground for the transmitter block.
19 TOUT- Inverted Modulation Current Output. Back-termination of 50to VCCT.
20 TOUT+ Noninverted Modulation Current Output. Back-termination of 50 to VCCT.
22 BIAS VCSEL Bias Current Output
23 FAULT
Transmitter Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high
even after the fault condition has been removed. A logic-low occurs when the fault condition has
been removed and the fault latch has been cleared by the DISABLE signal.
26 VEER Ground. Provides ground for the receiver block.
28 RIN- Inverted Receive Data Input, CML
29 RIN+ Noninverted Receive Data Input, CML
31 CAZ2
Offset Correction Loop Capacitor. A capacitor connected between this pin and CAZ1 sets the time
constant of the offset correction loop. The offset correction can be disabled through the digital
interface by setting the bit AZ_EN = 0.
32 CAZ1 Offset Correction Loop Capacitor. Counterpart to CAZ2, internally connected to VEER.
— EP Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical
performance (see the Exposed-Pad Package section).
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL DriverRPULL
RPULLRPULL
RPULL
VEER
VCCD
MAX3799
BIAS
MONITOR
OUTPUT
CONTROL
LOGIC
LOS
3-WIRE
INTERFACE
CONTROL
LOGIC
PULSE-
WIDTH
CONTROL
IVCSEL = IMOD - IDE
INTERNAL REGISTER
OFFSET
CORRECTION
4b DAC SET_TXDE
4b DAC SET_PWCTRL
9b DAC SET_IBIAS
9b DAC SET_IMOD
8b DAC SET_CML
6b DAC SET_LOS
RXDE_EN
TX_POL
CAZ1
RIN+
RSEL
SCL
SDA
CSEL
BIAS
TOUT+
TOUT-
FAULT
BMON
IBIAS
IMODIDE
RIN-
CAZ2
AZ_EN
SQ_EN
RATE_SEL
LOS_EN
TX_EN
LOS_POL
RX_POL
ROUT+
ROUT-
LOS
TIN+
TIN-
DISABLE
RPULL
VCCT
10.32Gbps LIMITING AMPLIFIER
10.32Gbps VCSEL DRIVER
EYE SAFETY AND
OUTPUT CONTROL
POWER-ON RESET900MHz
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Dual Path LimiterThe limiting amplifier features a low data-rate mode
(1.25Gbps) and a high data-rate mode (up to
10.32Gbps), allowing for overall system optimization.
Either the RSEL pin or the RATE_SEL bit can perform
the rate selection. For operating up to 1.25Gbps, the
low data-rate mode (RATE_SEL = 0) is recommended.
For operation up to 14.025Gbps, the high data-rate
mode (RATE_SEL = 1) is recommended. The polarity of
the ROUT+/ROUT- relative to RIN+/RIN- is pro-
grammed by the RX_POL bit.
Offset Correction CircuitryThe offset correction circuit is enabled to remove pulse-
width distortion caused by intrinsic offset voltages with-
in the differential amplifier stages. An external capacitor
(CAZ) connected between the CAZ1 and CAZ2 pins is
used to set the offset correction loop cutoff frequency.
The offset loop can be disabled using the AZ_EN bit.
CML Output Stage with Deemphasis
and Slew-Rate ControlThe CML output stage is optimized for differential 100Ω
loads. The RXDE_EN bit adds analog deemphasis
compensation to the limited differential output signal for
SFP connector losses. The output stage is controlled by
a combination of the RX_EN and SQ_EN bits and the
LOS pin. See Table 1.
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude range is from 40mVP-Pup to 1200mVP-Pwith
4.6mVP-Presolution (assuming an ideal 100Ωdifferen-
tial load).
Loss-of-Signal (LOS) CircuitryThe input data amplitude is compared to a preset
threshold controlled by the 6-bit DAC register
SET_LOS. The LOS assert level can be programmed
from 14mVP-Pup to 77mVP-P with 1.5mVP-Presolution
(assuming an ideal 100Ωdifferential source). LOS is
enabled through the LOS_EN bit and the polarity of the
LOS is controlled with the LOS_POL bit.
VCSEL DriverThe VCSEL driver inside the MAX3799 is designed to
operate from 1.0625Gbps to 10.32Gbps. The transmit-
ter contains a differential data path with pulse-width
adjustment, bias current and modulation current DACs,
output driver with programmable deemphasis, power-
on reset circuitry, BIAS monitor, VCSEL current limiter,
and eye safety circuitry. A 3-wire digital interface is
used to control the transmitter functions. The registers
that control the transmitter functionality are TXCTRL,
TXSTAT1, TXSTAT2, SET_IBIAS, SET_IMOD, IMOD-
MAX, IBIASMAX, MODINC, BIASINC, MODECTRL,
SET_PWCTRL, and SET_TXDE.
Differential Data PathThe CML input buffer is optimized for AC-coupled sig-
nals and is internally terminated with a differential
100Ω. Differential input data is equalized for high-fre-
quency losses due to SFP connectors. The TX_POL bit
in the TXCTRL register controls the polarity of TOUT+
and TOUT- vs. TIN+ and TIN-. The SET_PWCTRL regis-
ter controls the output eye-crossing adjustment. A sta-
tus indicator bit (TXED) monitors the presence of an AC
input signal.
RX_ENSQ_ENLOSOPERATION MODE
DESCRIPTIONX X CML output disabled.
1 0 X CML output enabled.
1 1 0 CML output enabled. 1 1 CML output disabled.
Table 1. CML Output Stage Operation Mode
RATE_SELOPERATION MODE DESCRIPTION 1.25Gbps operation with reduced output
edge speed. Up to 10.32Gbps operation.
Table 2. Slew-Rate Control for CML
Output Stage
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Bias Current DACThe bias current from the MAX3799 is optimized to pro-
vide up to 15mA of bias current into a 50Ωto 75Ω
VCSEL load with 40µA resolution. The bias current is
controlled through the 3-wire digital interface using the
SET_IBIAS, IBIASMAX, and BIASINC registers.
For VCSEL operation, the IBIASMAX register is first pro-
grammed to a desired maximum bias current value (up
to 15mA). The bias current to the VCSEL then can
range from zero to the value programmed into the
IBIASMAX register. The bias current level is stored in
the 9-bit SET_IBIAS register. Only bits 1 to 8 are written
to. The LSB (bit 0) of SET_IBIAS is initialized to zero
and is updated through the BIASINC register.
The value of the SET_IBIAS DAC register is updated
when the BIASINC register is addressed through the
3-wire interface. The BIASINC register is an 8-bit regis-
ter where the first 5 bits contain the increment informa-
tion in two’s complement notation. Increment values
range from -8 to +7 LSBs. If the updated value of
SET_IBIAS[8:1] exceeds IBIASMAX[7:0], the IBIASERR
warning flag is set and SET_IBIAS[8:0] remains
unchanged.
Modulation Current DACThe modulation current from the MAX3799 is optimized
to provide up to 12mA of modulation current into a
100Ωdifferential load with 40µA resolution. The modu-
lation current is controlled through the 3-wire digital
interface using the SET_IMOD, IMODMAX, MODINC,
and SET_TXDE registers.
For VCSEL operation, the IMODMAX register is first pro-
grammed to a desired maximum modulation current
value (up to 12mA into a 100Ωdifferential load). The
modulation current to the VCSEL then can range from
zero to the value programmed into the IMODMAX regis-
ter. The modulation current level is stored in the 9-bit
SET_IMOD register. Only bits 1 to 8 are written to. The
LSB (bit 0) of SET_IMOD is initialized to zero and is
updated through the MODINC register.
The value of the SET_IMOD DAC register is updated
when the MODINC register is addressed through the
3-wire interface. The MODINC register is an 8-bit regis-
ter where the first 5 bits contain the increment informa-
tion in two’s complement notation. Increment values
range from -8 to +7 LSBs. If the updated value of
SET_IMOD[8:1] exceeds IMODMAX[7:0], the IMODERR
warning flag is set and SET_IMOD[8:0] remains
unchanged.
Output DriverThe output driver is optimized for an AC-coupled 100Ω
differential load. The output stage also features program-
mable deemphasis that allows the deemphasis ampli-
tude to be set as a percentage of the modulation current.
The deemphasis function is enabled by the TXDE_EN
bit. At initial setup, the required amount of deemphasis
can be set using the SET_TXDE register. During the
system operation, it is advised to use the incremental
mode that updates the deemphasis (SET_TXDE) and
the modulation current DAC (SET_IMOD) simultaneous-
ly through the MODINC register.
Power-On Reset (POR)Power-on reset ensures that the laser is off until the
supply voltage has reached a specified threshold
(2.55V). After power-on reset, bias current and modula-
tion current ramp up slowly to avoid an overshoot. In
the case of a POR, all registers are reset to their default
values.
Bias Current MonitorCurrent out of the BMON pin is typically 1/16th the
value of IBIAS. A resistor to ground at BMON sets the
voltage gain. An internal comparator latches a SOFT
FAULT if the voltage on BMON exceeds the value of
VCC- 0.55V.
Eye Safety and Output Control CircuitryThe safety and output control circuitry contains a dis-
able pin (DISABLE) and disable bit (TX_EN), along with
a FAULT indicator and fault detectors (Figure 3). The
MAX3799 has two types of faults, HARD FAULT and
SOFT FAULT. A HARD FAULT triggers the FAULT pin
and the output to the VCSEL is disabled. A SOFT
FAULT operates more like a warning and the outputs
are not disabled. Both types of faults are stored in the
TXSTAT1 and TXSTAT2 registers.
The FAULT pin is a latched output that can be cleared
by toggling the DISABLE pin. Toggling the DISABLE
pin also clears the TXSTAT1 and TXSTAT2 registers. A
single-point fault can be a short to VCCor GND. Table
3 shows the circuit response to various single-point
failures.
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver<0>
<1>
0.72V
<2>
0.8V
<3>
1.5V
<4>
<5>
<6>
<7>
POR
VCC - 0.55V
FAULT
FAULT REGISTER
TXSTAT1
<1>
<0>UNUSED
TX_LOS
BIAS INCREMENT
BIASMAX
MOD INCREMENT
MODMAX
LOSS-OF-SIGNAL
CIRCUIT
<2>
<3>
WARNING REGISTER
TXSTAT2
ADDR7
VCCT
TOUT-
TOUT+
IMOD
IBIAS
IBIAS
BIAS
VCCT
DISABLE
8kΩ
BMON
RESETPOR
FAULT REGISTER TXSTAT1
