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MAX5072ETJ+
2.2MHz, Dual-Output Buck or Boost Converter with POR and Power-Fail Output
General DescriptionThe MAX5072 is a dual-output DC-DC converter with inte-
grated high-side n-channel power MOSFETs. Each output
can be configured either as a buck converter or a boost
converter. The MAX5072 is designed to manage the
power requirements of xDSL modems. The wide 5.5V to
23V input voltage range allows for the use of inexpensive
AC adapters to power the device in xDSL modem appli-
cations. Each output is programmable down to 0.8V in the
buck mode and up to 28V in the boost mode with an out-
put voltage accuracy of ±1%. In the buck mode, convert-
er 1 and converter 2 can deliver 2A and 1A, respectively.
The output switching frequency of each converter can be
programmed from 200kHz to 2.2MHz to avoid harmonics
in the xDSL frequency band of operation. Each output
operates 180°out-of-phase, thus reducing input-capaci-
tor ripple current, size, and cost. A SYNC input facilitates
external frequency synchronization. Moreover, a CLKOUT
output provides out-of-phase clock signal with respect to
converter 2, allowing four-phase operation using two
MAX5072 ICs in master-slave configuration.
The MAX5072 includes an internal digital soft-start that
reduces inrush current, eliminates output-voltage over-
shoot, and ensures monotonic rise in output voltage dur-
ing power-up. The device includes a power-good output
and power-on reset as well as manual reset. In addition,
each converter output can be shut down individually. The
MAX5072 features a "dying gasp" output, which goes low
when the input voltage drops below a preprogrammed
voltage. Protection features include output short-circuit
protection for buck mode and maximum duty-cycle limit
for boost operation, as well as thermal shutdown.
The MAX5072 is available in a thermally enhanced 32-pin
thin QFN package that can dissipate 2.7W at +70°C ambi-
ent temperature. The device is rated for operation over the
-40°C to +85°C extended, or -40°C to +125°C automotive
temperature range.
ApplicationsxDSL Modems
xDSL Routers
Point-of-Load DC-DC Converters
Features4.5V to 5.5V or 5.5V to 23V Input Supply Voltage
Range0.8V (Buck) to 28V (Boost) Output VoltageTwo Independent Output DC-DC Converters with
Internal Power MOSFETsEach Output can be Configured in Buck or Boost
ModeIOUT1and IOUT2of 2A and 1A (Respectively) in
Buck Mode180°Out-of-Phase OperationClock Output for Four-Phase OperationSwitching Frequency Programmable from 200kHz
to 2.2MHzDigital Soft-Start and Independent Converter
ShutdownSYNC Input, Power-On Reset, Manual Reset, And
Power-Fail OutputShort-Circuit Protection (Buck)/Maximum Duty-
Cycle Limit (Boost)Thermal ShutdownThermally Enhanced 32-Pin Thin QFN Package
Dissipates up to 2.7W at +70°C
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
Pin Configuration
Ordering Information19-3503; Rev 2; 2/06
EVALUATION KIT
AVAILABLE232221201918
MAX5072
THIN QFNTOP VIEW
SOURCE1
PGOOD1
SOURCE1
PGND
SGND
PGND
SOURCE2SOURCE2
FSEL1BST1/VDD1DRAIN1DRAIN1EN1FB1COMP1
RST
BYPASS
OSC
PFISYNC
COMP2
FB2
PFOEN2
DRAIN2DRAIN2
BST2/VDD2
CLKOUT
PARTTEMP RANGEPIN-PACKAGEPKG
CODEMAX5072ETJ-40°C to +85°C32 Thin QFN-EP*
(5mm x 5mm)T3255-4
*EP = Exposed pad.
Ordering Information continued at end of data sheet.
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL= 0, PGND = SGND, CBYPASS= 0.22µF, CVL= 4.7µF (ceramic),
ROSC= 10kΩ(circuit of Figure 1), TA= TJ= TMINto TMAX, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to PGND............................................................-0.3V to +25V
SGND to PGND.....................................................-0.3V to +0.3V
VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V)
BST1/VDD1, BST2/VDD2, DRAIN_, PFO, RST, PGOOD1 to
SGND.................................................................-0.3V to +30V
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V
SOURCE_ to SGND................................................-0.6V to +25V
EN_ to SGND................................................-0.3V to (VL + 0.3V)
CLKOUT, BYPASS, OSC, FSEL1, COMP1,
COMP2, PFI, MR, SYNC, FB_ to SGND....-0.3V to (VL + 0.3V)
SOURCE1, DRAIN1 Peak Current..............................5A for 1ms
SOURCE2, DRAIN2 Peak Current..............................3A for 1ms
VL, BYPASS to SGND Short Circuit............................Continuous
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C above +70°C).....2758mW*
Package Junction-to-Case Thermal Resistance (θJC).......2°C/W
Operating Temperature Ranges:
MAX5072ETJ (TMINto TMAX)...........................-40°C to +85°C
MAX5072ATJ (TMINto TMAX).........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
*As per JEDEC51 standard.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SYSTEM SPECIFICATIONS(Note 2)5.523Input Voltage RangeV+VL = V+4.55.5V
Operating Supply CurrentIQVL unloaded, no switching,
VFB_ = 1V, V+ = 12V, ROSC = 60kΩ2.21.2mA
EN_ = 0, MR, PFO, and PGOOD_ floating,
V+ = 12V, ROSC = 60kΩ (MAX5072ETJ) 0.61.4
V+ Standby Supply CurrentISTBY
EN_ = 0, MR, PFO, and PGOOD_ floating,
V+ = 12V, ROSC = 60kΩ (MAX5072ATJ)0.61.4
V+ = VL = 5V82
V+ = 12V80Efficiencyη
VOUT1 = 3.3V at 1.5A,
VOUT2 = 2.5V at 0.75A
(fSW = 1.25MHz)V+ = 16V78
STARTUP/VL REGULATORVL Undervoltage Lockout Trip
LevelUVLOVL falling3.954.14.25V
VL Undervoltage Lockout
Hysteresis175mV
VL Output VoltageVLV+ = 5.5V to 23V, ISOURCE = 0 to 40mA4.95.25.5V
BYPASS OUTPUTIBYPASS = 0, ROSC = 60kΩ (MAX5072ETJ)1.982.002.02BYPASS VoltageVBYPASSIBYPASS = 0, ROSC = 60kΩ (MAX5072ATJ)1.9752.002.025V
BYPASS Load RegulationΔVBYPASS0 ≤ IBYPASS ≤ 50µA, ROSC = 60kΩ0210mV
SOFT-STARTDigital Ramp PeriodInternal 6-bit DAC2048
fOSC
clock
cycles
Soft-Start Steps64steps
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ELECTRICAL CHARACTERISTICS (continued)(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL= 0, PGND = SGND, CBYPASS= 0.22µF, CVL= 4.7µF (ceramic),
ROSC= 10kΩ(circuit of Figure 1), TA= TJ= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VOLTAGE-ERROR AMPLIFIERFB_ Input Bias CurrentIFB250nA
0°C ≤ TA ≤+70°C0.7920.80.808
-40°C ≤ TA ≤+85°C0.7880.80.812FB_ Input Voltage Set Point
-40°C ≤ TJ ≤+125°C (MAX5072ATJ only)0.7880.80.812
0°C to +85°C1.252.002.70
-40°C to +85°C1.22.02.9FB_ to COMP_
TransconductancegM
-40°C to +125°C (MAX5072ATJ only)1.22.02.9
INTERNAL MOSFETSISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5072ETJ)
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5072ATJ)
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5072ETJ)
On-Resistance Converter 1RON1
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5072ATJ)
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 5.2V330630
On-Resistance Converter 2RON2
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 4.5V350690
Minimum Converter 1 Output
CurrentIOUT1VOUT1 = 3.3V, V+ = 12V (Note 3)2A
Minimum Converter 2 Output
CurrentIOUT2VOUT2 = 2.5V, V+ = 12V (Note 3)1A
Converter 1 MOSFET Leakage
CurrentILK1EN1 = 0V, VDS = 23V10µA
Converter 2 MOSFET Leakage
CurrentILK2EN2 = 0V, VDS = 23V10µA
INTERNAL SWITCH CURRENT LIMITV+ = 12V (MAX5072ETJ)2.334.3Current-Limit Converter 1ICL1V+ = 12V (MAX5072ATJ)2.334.6A
MAX5072ETJ1.381.82.10Current-Limit Converter 2ICL2MAX5072ATJ1.381.82.10A
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ELECTRICAL CHARACTERISTICS (continued)(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL= 0, PGND = SGND, CBYPASS= 0.22µF, CVL= 4.7µF (ceramic),
ROSC= 10kΩ(circuit of Figure 1), TA= TJ= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL OSCILLATOR/SYNCSYNC = SGND, fSW = 1.25MHz848695Maximum Duty CycleDMAXSYNC = SGND, fSW = 2.2MHz848695%
Switching Frequency RangefSWEach converter2002200kHz
Switching FrequencyfSETROSC = 10kΩ, each converter112512501375kHz
Switching Frequency Accuracy5.6kΩ ≤ ROSC ≤ 56kΩ, 1%, each converter-15+15%
SYNC Frequency RangefSYNCSYNC input frequency is twice the
individual converter frequency4004400kHz
SYNC High ThresholdVSYNCH2.4V
SYNC Low ThresholdVSYNCL0.8V
SYNC Input MIN Pulse WidthtSYNCIN100ns
Clock Output Phase DelayCLKOUT
PHASE
ROSC = 60kΩ, 1%, with respect to
converter 2/SOURCE2 waveform45degrees
SYNC to SOURCE 1 Phase DelaySYNCPHASEROSC = 60kΩ, 1%45degrees
Clock Output High LevelVCLKOUTHVL = 5.2V, sourcing 5mA4V
Clock Output Low LevelVCLKOUTLVL = 5.2V, sinking 5mA0.4V
FSEL1FSEL1 Input High ThresholdVIHV+ = VL = +5.2V2.4V
FSEL1 Input Low ThresholdVILV+ = VL = +5.2V0.8V
EN_ INPUTSEN_ Input High ThresholdVIHV+ = VL = +5.2V2.41.8V
EN_ Input Low ThresholdVILV+ = VL = +5.2V1.20.8V
EN_ Bias CurrentIB(EN)250nA
MANUAL RESET (MR) AND POWER-ON-RESET (RST)MR Minimum Pulse WidthtMR10µs
MR Glitch ImmunityMaximum glitch pulse width allowed for
RST to remain high100ns
MR to RST Propagation DelaytMD1µs
MR Input High ThresholdVIHV+ = VL = +5.2V2.4V
MR Input Low ThresholdVILV+ = VL = +5.2V0.8V
MR Internal Pullup ResistorRMR44kΩ
Power-On-Reset ThresholdVTHRST goes high 180ms after VOUT1 and
VOUT2 cross this threshold9092.595% VOUT
FB_ to RST Propagation DelaytFDFB overdrive from 0.8V to 0.6V1.1µs
RST Active Timeout PeriodtRP140200360ms
ISINK = 3mA (MAX5072ETJ)0.4RST Output VoltageVRST_ISINK = 3mA (MAX5072ATJ)0.52V
RST Output Leakage CurrentIRSTLKV+ = VL = 5.2V, VRST = 23V, VFB_ = 0.8V1µA
MAX5072
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ELECTRICAL CHARACTERISTICS (continued)(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL= 0, PGND = SGND, CBYPASS= 0.22µF, CVL= 4.7µF (ceramic),
ROSC= 10kΩ(circuit of Figure 1), TA= TJ= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER-GOOD OUTPUT (PGOOD1)PGOOD1 ThresholdPGOOD1VTHPGOOD1 goes high after VOUT crosses
PGOOD1 threshold9092.595% VOUT
ISINK = 3mA (MAX5072ETJ)0.4PGOOD1 Output VoltageVPGOOD1ISINK = 3mA (MAX5072ATJ)0.52VGO OD 1 O utp ut Leakag e C ur r entILKP GOOD 1V + = V L = 5.2V , V P GOOD 1 = 23V , V F B1 = 1V 1µA
DYING GASP POWER-FAIL INPUT (PFI), POWER-FAIL OUTPUT (PFO)PFI Trip LevelVTHPFI falling0.760.780.80V
PFI HysteresisVTHH20mV
PFI Input Bias CurrentIB(PFI)VPFI = 0.75V500nA
PFI Glitch Immunity100mV overdrive35µs
PFI to PFO Propagation DelaytPFD50mV overdrive35µs
ISINK = 3mA (MAX5072ETJ)0.4PFO Output Low VoltageVPFOISINK = 3mA (MAX5072ATJ)0.52V
PFO Output Leakage CurrentILKPFOV+ = VL = 5.2V, VPFO = 5.5V, VPFI = 1V1µA
THERMAL MANAGEMENTThermal ShutdownTSHDNJunction temperature+150°C
Thermal HysteresisTHYSTJunction temperature30°C
Note 1:Specifications at -40°C are guaranteed by design and not production tested.
Note 2:Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation.
Note 3:Output current may be limited by the power dissipation of the package, see the Power Dissipationsection in the
Applications Information.
