MAX5885EGM+D ,3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36B1 B12Base Stations: Single/Multicarrier UMTS, 2 35B0 B13CDMA, GSM XOR 3 34 B14Comm ..
MAX5886EGK ,3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPN.C. 1 51 B7NBase Stations: Single/Multicarrier UMTS, N.C. 2 50 B7PN.C. 3 49 B8NCDMA, ..
MAX5886EGK+D ,3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPN.C. 1 51 B7NBase Stations: Single/Multicarrier UMTS, N.C. 2 50 B7PN.C. 3 49 B8NCDMA, ..
MAX5887EGK ,3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPBase Stations: Single/Multicarrier UMTS, B1P 1 51 B9NB1N 2 50 B9PCDMA, GSM B0P 3 49 B ..
MAX5887EGK+D ,3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPBase Stations: Single/Multicarrier UMTS, B1P 1 51 B9NB1N 2 50 B9PCDMA, GSM B0P 3 49 B ..
MAX5888AEGK ,3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPB3P 1 51 B11NBase Stations: Single-/Multicarrier UMTS, B3N 2 50 B11PB2P 3 49 B12NCDMA ..
MAZ8051-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8051-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8051M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-M ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAX5885EGM+D
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs
General DescriptionThe MAX5885 is an advanced, 16-bit, 200Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 77dBc spurious-free dynamic
range (SFDR) at fOUT= 10MHz. The DAC supports
update rates of 200Msps at a power dissipation of less
than 200mW.
The MAX5885 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1VP-Pand 1VP-P.
The MAX5885 features an integrated 1.2V bandgap
reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5885 are
designed for CMOS-compatible voltage levels. The
MAX5885 is available in a 48-pin QFN package with an
exposed paddle (EP) and is specified for the extended
industrial temperature range (-40°C to +85°C).
Refer to the MAX5883 and MAX5884 data sheets for
pin-compatible 12- and 14-bit versions of the MAX5885.
For LVDS high-speed versions, refer to the MAX5886/
MAX5887/MAX5888 data sheet.
ApplicationsBase Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features200Msps Output Update RateSingle 3.3V Supply OperationExcellent SFDR and IMD Performance
SFDR = 77dBc at fOUT= 10MHz (to Nyquist)
IMD = -88dBc at fOUT= 10MHz
ACLR = 74dB at fOUT= 30.72MHz2mA to 20mA Full-Scale Output CurrentCMOS-Compatible Digital and Clock InputsOn-Chip 1.2V Bandgap ReferenceLow Power Dissipation48-Pin QFN-EP Package
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Ordering Information19-2786; Rev 1; 12/03
PARTTEMP RANGEPIN-PACKAGEMAX5885EGM-40°C to +85°C48 QFN-EP*
B12
B13
B15
DGND
N.C.
N.C.
N.C.
N.C.
N.C.
DVDD
SEL0
B14XOR
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
AVDD
AGND1
AGND
IOUTNIOUTP
AGND
AGND
N.C.
DACREF
FSADJ
REFIOB4B5B6DV
DGNDB7B8B9B11B10B2
QFNMAX5885
AGND
TOP VIEW47464544434241403938371415161718192021222324
Pin Configuration*EP = Exposed paddle.
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA,
fCLK= 200Msps, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AVDD, DVDD, VCLK to DGND...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0–B15, SEL0, PD, XOR to DGND.............-0.3V to DVDD+ 0.3V
Continuous Power Dissipation (TA= +70°C)
48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW
Thermal Resistance (θJA)..............................................+37°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution16Bits
Integral NonlinearityINLMeasured differentially±0.006%FS
Differential NonlinearityDNLMeasured differentially±0.003%FS
Offset ErrorOS-0.025±0.003+0.025%FS
Offset Drift±50ppm/°C
Full-Scale Gain ErrorGEFSExternal reference, TA ≥ +25°C-3.5+1.3%FS
Internal reference±100Gain DriftExternal reference±50ppm/°C
Full-Scale Output CurrentIOUT(Note 1)220mA
Min Output VoltageSingle ended-0.5V
Max Output VoltageSingle ended1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
DYNAMIC PERFORMANCEOutput Update RatefCLK1200Msps
fCLK = 100MHzfOUT = 16MHz, -12dB FS-155Noise Spectral DensityfCLK = 200MHzfOUT = 80MHz, -12dB FS-148
dB FS/
fOUT = 1MHz, 0dB FS88
fOUT = 1MHz, -6dB FS83Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 100MHz
fOUT = 1MHz, -12dB FS80
dBc
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA,
fCLK= 200Msps, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfOUT = 10MHz, -12dB FS77fCLK = 100MHzfOUT = 30MHz, -12dB FS73
fOUT = 10MHz, -12dB FS72
fOUT = 16MHz, -12dB FS,
TA ≥+25°C6876
fOUT = 30MHz, -12dB FS71
Spurious-Free Dynamic Range to
NyquistSFDR
fCLK = 200MHz
fOUT = 50MHz, -12dB FS71
dBc
fOUT1 = 9MHz, -6dB FSfCLK = 100MHzfOUT2 = 10MHz, -6dB FS-88
fOU T 1 = 29M H z, - 6d B FS Two-Tone IMDTTIMD
fCLK = 200MHzfOU T 2 = 30M H z, - 6d B FS -74
dBc
Four-Tone IMD, 1MHz Frequency
Spacing, GSM ModelFTIMDfCLK = 150MHzfOUT = 31.99MHz,
-12dB FS-82dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLRfCLK =
184.32MHzfOUT = 30.72MHz74dB
Output BandwidthBW-1dB(Note 2)450MHz
REFERENCEInternal Reference Voltage RangeVREFIO1.11.211.34V
Reference Input Compliance
RangeVREFIOCR0.1251.25V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage DriftTCOREF±50ppm/°C
ANALOG OUTPUT TIMINGOutput Fall TimetFALL90% to 10% (Note 3)375ps
Output Rise TimetRISE10% to 90% (Note 3)375ps
Output Voltage Settling TimetSETTLEOutput settles to 0.025% FS (Note 3)11ns
Output Propagation DelaytPD(Note 3)1.8ns
Glitch Energy1pV-s
IOUT = 2mA30Output NoiseNOUTIOUT = 20mA30pA/√Hz
TIMING CHARACTERISTICSData to Clock Setup TimetSETUPReferenced to rising edge of clock (Note 4)0.4ns
Data to Clock Hold TimetHOLDReferenced to rising edge of clock (Note 4)1.25ns
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Note 1:Nominal full-scale current IOUT= 32 ✕IREF.
Note 2:This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885.
Note 3:Parameter measured single ended into a 50Ωtermination resistor.
Note 4:Parameter guaranteed by design.
Note 5:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA,
fCLK= 200Msps, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSData Latency3.5Clock
cycles
Minimum Clock Pulse Width HightCHCLKP, CLKN1.5ns
Minimum Clock Pulse Width LowtCLCLKP, CLKN1.5ns
CMOS LOGIC INPUTS (B0–B15, PD, SEL0, XOR)Input Logic HighVIH0.7 x
DVDDV
Input Logic LowVIL0.3 x
DVDDV
Input Leakage CurrentIIN-15+15µA
Input CapacitanceCIN5pF
CLOCK INPUTS (CLKP, CLKN)Sine wave≥1.5Differential Input Voltage SwingVCLKSquare wave≥0.5VP-P
Differential Input Slew RateSRCLK(Note 5)>100V/µs
Common-Mode Voltage RangeVCOM1.5
±20%V
Input ResistanceRCLK5kΩ
Input CapacitanceCCLK5pF
POWER SUPPLIESAnalog Supply Voltage RangeAVDD3.1353.33.465V
Digital Supply Voltage RangeDVDD3.1353.33.465V
Clock Supply Voltage RangeVCLK3.1353.33.465V
fCLK = 100Msps, fOUT = 1MHz27Analog Supply CurrentIAVDDPower-down0.3mA
fCLK = 100Msps, fOUT = 1MHz8.5mADigital Supply CurrentIDVDDPower-down10µA
fCLK = 100Msps, fOUT = 1MHz5.5mAClock Supply CurrentIVCLKPower-down10µA
fCLK = 100Msps, fOUT = 1MHz135Power DissipationPDISSPower-down1mW
Power-Supply Rejection RatioPSRRAVDD = VCLK = DVDD = 3.3V ±5% (Note 5)-0.1+0.1%FS/V
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Typical Operating Characteristics(AVDD= DVDD= VCLK = 3.3V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 50MHz)
MAX5885 toc01
fOUT (MHz)
SFDR (dBc)
-12dB FS
0dB FS-6dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5885 toc02
fOUT (MHz)
SFDR (dBc)
-6dB FS
-12dB FS0dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 150MHz)
MAX5885 toc03
fOUT (MHz)
SFDR (dBc)
-12dB FS
0dB FS-6dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5885 toc04
fOUT (MHz)
SFDR (dBc)30706050
-12dB FS
0dB FS
-6dB FS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 100MHz)
MAX5885 toc05
fOUT (MHz)
TWO-TONE IMD (dBc)2050
-12dB FS
-6dB FS40-100
TWO-TONE INTERMODULATION DISTORTION
(fCLK = 100MHz)
MAX5885 toc06
fOUT (MHz)
OUTPUT POWER (dBm)293231
2 x fT1 - fT2
fT1 fT2
fT1 = 28.9429MHz
fT2 = 29.8706MHz
2 x fT2 - fT1
AOUT = -6dB FS
BW = 12MHz
SFDR vs. OUTPUT FREQUENCY
(fCLK = 200MHz, AOUT = -6dB FS)
MAX5885 toc08
fOUT (MHz)
SFDR (dBc)
IOUT = 5mAIOUT = 10mA
IOUT = 20mA
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 200MHz)
MAX5885 toc07
fOUT (MHz)
TWO-TONE IMD (dBc)103080
-12dB FS
-6dB FS607050
SFDR vs. fOUT AND TEMPERATURE
(fCLK = 200MHz, AOUT = -6dB FS, IFS = 20mA)
MAX5885 toc09
fOUT (MHz)
SFDR (dBc)306050
TA = -40°C
TA = +25°CTA = +85°C
