MC10H121FNR2 ,4-Wide OR-AND/OR-ANDbar GateAPPLICATION NOTEDifferential Characteristics (continued)APPLICATION NOTE USAGEThis application note ..
MC10H121FNR2 ,4-Wide OR-AND/OR-ANDbar Gate2MC10H121PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
MC10H121FNR2 ,4-Wide OR-AND/OR-ANDbar GateAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC10H121L ,4-Wide OR-AND/OR-AND GateMAXIMUM RATINGSCharacteristic Symbol Rating Unit
MC10H121P ,4-Wide OR-AND/OR-ANDbar Gate
MC10H121P ,4-Wide OR-AND/OR-ANDbar Gate**SEMICONDUCTOR TECHNICAL DATA * The MC10H121 is a basic logic building block providing the simulta ..
MC34167T ,Power Switching RegulatorMAXIMUM RATINGSRating Symbol Value UnitPower Supply Input Voltage V 40 VCCSwitch Output Voltage Ran ..
MC34167TG , 5.0 A, Step−Up/Down/Inverting Switching Regulators
MC34167TH ,POWER SWITCHING REGULATORSfeatures consist of cycle–by–cycle current limiting,undervoltage lockout, and thermal shutdown. Als ..
MC34167TV ,POWER SWITCHING REGULATORSOrder this document by MC34167/D* *The MC34167, MC33167 series are high performance fixed frequenc ..
MC34167TVG , 5.0 A, Step−Up/Down/Inverting Switching Regulators
MC34181D ,Low Power, High Slew Rate, Wide Bandwidth, JFET Input Operational AmplifiersELECTRICAL CHARACTERISTICS (V = +15 V, V = –15 V, T = 25°C, unless otherwise noted.)CC EE ACharacte ..
MC10H121FNR2
4-Wide OR-AND/OR-ANDbar Gate
-The MC10H121 is a basic logic building block providing the
simultaneous OR–AND/OR–AND–Invert function, useful in data
control and digital multiplexing applications. This MECL 10H part is
a functional/pinout duplication of the standard MECL 10K family
part, with 100% improvement in propagation delay, and no increase in
power– supply current. Propagation Delay, 1.0 ns Typical Power Dissipation 100 mW/Gate Typical (same as MECL 10K) Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENTVCC1
AOUT
AOUT
A1IN
A1IN
A1IN
A2IN
VEE
VCC2
A4IN
A4IN
A4IN
A3IN
A3IN
A2IN, A3IN
A2IN
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Pin assignment is for Dual–in–Line Package.
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ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620A
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
